• Journal of IKEEE
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• v.24 no.4
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• pp.1184-1187
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• 2020

This paper proposes an in-vehicle network controller fully exploiting the advantages of UART (Universal Asynchronous Receiver/Transmitter) and CAN (Controller Area Network). UART is used in 1-to-1 communication and it exploits parity bit for data integrity check. The proposed in-vehicle network controller converts UART into CAN, which enables multiple communications along with 1-to-1 communication. Also, the proposed in-vehicle network controller exploits CRC (cyclic redundancy check) for data integrity check, which increases communication reliability. CAN is controlled by microprocessor, but the proposed in-vehicle network controller can be controlled by any devices compliant with RS-232, RS-422, and RS-485.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.11
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• pp.972-978
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• 2012

LDPC (low density parity check) code shows near Shannon limit performance by iterative decoding based on sum-product algorithm (SPA). Message updating procedure between variable and check nodes in SPA is done by a scheduling method. LDPC code shows different performance according to scheduling schemes. The conventional researches have been shown that the shuffled BP (belief propagation) algorithm shows better performance than the standard BP algorithm although it needs less number of iterations. However the reason is not analyzed clearly. Therefore the reason of difference in performance according to LDPC decoding algorithms is analyzed in this paper. 4 cases according to satisfaction of parity check condition are considered and compared. As results, the difference in the updating procedure in a cycle in the parity check matrix is considered to be the main reason of performance difference.

• 전자공학회논문지 IE
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• v.43 no.4
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• pp.115-121
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• 2006

In this paper, we proposed about data error check and correction on channel transmission in the communication system. LDPC codes are used for minimizing channel errors by modeling AWGN Channel as a VDSL system. Because LDPC Codes use low density parity bit, mathematical complexity is low and relating processing time becomes shorten. Also the performance of LDPC code is better than that of turbo code in long code word on iterative decoding algorithm. This algorithm is better than conventional algorithms to correct errors, the proposed algorithm assigns weights for errors concerning parity bits. The proposed weighted Bit-flipping algorithm is better than the conventional Bit-flipping algorithm and we are recognized improve gain rate of 1 dB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.12C
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• pp.1135-1141
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• 2007

In this paper, an adaptive bit-reliability mapping is proposed for the bit-level Chase combining in LDPC-coded high-order modulation systems. Contrary to the previously known bit-reliability mapping that assigns the information (or parity) bits to more (or less) reliable bit positions, the proposed mapping adaptively assigns codeword bits to the bit positions of various reliabilities by considering the characteristics of code and protection levels of bits in high-order modulation symbol. Compared with the symbol-level Chase combining and the constellation rearrangement bit mapping, the proposed mapping gives $0.7{\sim}1.3$ dB and $0.1{\sim}1.0$ dB performance gain at $FER=10^{-3}$ with no additional complexity, respectively. Adaptive bit-reliability mappings are derived for various environments and the validity of them is confirmed through simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.11
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• pp.952-960
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• 2012

In the distributed video coding (DVC) system, the difference between the side information and the original Wyner-Ziv frame is corrected using channel codes and the additional parity bits are requested through feedback channel if the error is not corrected. The efficient bit rate control is important to use the DVC system in the band-limited channel, such as mobile communication environments. In this paper, the constant bit rate control method in the encoder of the DVC system is proposed. The coding performance as well as the bit rate is efficiently controlled by the proposed method.

• Journal of Broadcast Engineering
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• v.16 no.4
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• pp.635-646
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• 2011

In distributed video coding, low complexity encoder can be realized by shifting encoder-side complex processes to decoder-side. However, not only motion estimation/compensation processes but also complex LDPC decoding process are imposed to the Wyner-Ziv decoder, therefore decoder-side complexity has been one important issue to improve. LDPC decoding process consists of numerous iterative decoding processes, therefore complexity increases as the number of iteration increases. This iterative LDPC decoding process accounts for more than 60% of whole WZ decoding complexity, therefore it can be said to be a main target for complexity reduction. Previously, HDA (Hard Decision Aided) method is introduced for fast LDPC decoding process. For currently received parity bits, HDA method certainly reduces the complexity of decoding process, however, LDPC decoding process is still performed even with insufficient amount of parity request which cannot lead to successful LDPC decoding. Therefore, we can further reduce complexity by avoiding the decoding process for insufficient parity bits. In this paper, therefore, a parity request estimation method is proposed using bit plane-wise correlation and temporal correlation. Joint usage of HDA method and the proposed method achieves about 72% of complexity reduction in LDPC decoding process, while rate distortion performance is degraded only by -0.0275 dB in BDPSNR.

• Journal of the Korea Society of Computer and Information
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• v.12 no.4
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• pp.87-94
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• 2007

Imbalances in focus, luminance and color between stereo Pairs could cause disparity vector estimation error and increment of transmission data. If the distribution of errors in residual image is large, it may influence to lowering of compression performance. Therefore, in this paper, we propose an efficient balancing method between stereo pairs to reduce the effect. For this, we registrated stereo images using a FFT based method to consider the pixels in the occluded region, we eliminated the pixels of blocks which has large error of disparity vector estimation in balancing function estimation. The balancing function has estimated using histogram specification, local information of target image and residual image between stereo images. Experiments show that the proposed method is effective in error distribution, PSNR and disparity vector estimation. We expect that our method can be improving compression efficiency in stereo coding system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.8
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• pp.662-668
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• 2013

Mobile communication systems have been adopting link adaptive transmission schemes such as adaptive modulation and coding (AMC) and hybrid-ARQ (HARQ). Incremental redundancy (IR) HARQ scheme is known to be highly efficient in terms of throughput and power consumption and can be a good solution for mobile communication systems. In this paper, we propose an IR-HARQ scheme based on dual-diagonal parity-type block LDPC codes in which we define a transmission priority of coded bits and propose the sub-packet construction rule. We present the throughput performance of IR-HARQ with various modulation and coding and multi-antenna modes. Consequently, the proposed scheme provides the improvement of system throughput by elaborate link adaptation with CQI information.

• Convergence Security Journal
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• v.12 no.4
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• pp.85-90
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• 2012

DES is a 64-bit binary, and each block is divided into units of time are encrypted through an encryption algorithm. The same key as the symmetric algorithm for encryption and decryption algorithms are used. Conversely, when decryption keys, and some differences may apply. The key length of 64 bits are represented by two ten thousand an d two 56-bit is actually being used as the key remaining 8 bits are used as parity check bits. The 64-bit block and 56-bit encryption key that is based on a total of 16 times 16 modifier and spread through the chaos is completed. DES algorithm was chosen on the strength of the password is questionable because the most widely available commercially, but has been used. In addition to the basic DES algorithm adopted in the future in the field by a considerable period are expected to continue to take advantage of the DES algorithm effectively measures are expected to be in the field note.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.405-409
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• 2009

In this paper, the effects of LLR (Log-Likelihood Ratio) approximation on LDPC (Low-Density Parity-Check) decoder performance are analyzed, and optimal design conditions of LDPC decoder are derived. The min-sum LDPC decoding algorithm which is based on an approximation of LLR sum-product algorithm is modeled and simulated by MATLAB, and it is analyzed that the effects of LLR approximation bit-width and maximum iteration cycles on the bit error rate (BER) performance of LDCP decoder. The parity check matrix for IEEE 802.11n standard which has block length of 1,944 bits and code rate of 1/2 is used, and AWGN channel with QPSK modulation is assumed. The simulation results show that optimal BER performance is achieved for 7 iteration cycles and LLR bit-width of (7,5).