• Journal of IKEEE
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• v.17 no.4
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• pp.537-543
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• 2013

This paper proposed a low EMI spread spectrum clock generator (SSCG) using discontinuous frequency modulation technique. The proposed SSCG is designed for triangular frequency modulation with high modulation depth. When the maximum time interval error (MTIE) of the SSCG is higher than given limit, the output frequency of SSCG is divided by two and used for reducing the time interval error (TIE). This discontinuous frequency modulation technique can effectively reduce the EMI within given limit. The simulated EMI of proposed SSCG was reduced by 18.5dB than that of conventional methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.21-31
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• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.565-568
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• 2000

본 논문에서는 data-driven 반향제거기 구조에서 타이밍 지터의 보상 방법을 제안한다. V.90PCM 모뎀환경에서 네트윅 클록에 동기가 되어 동작하는 사용자 터미널 모뎀이 디지털 PLL (DPLL)을 이용하여 타이밍 복원을 하면 타이밍 지터 성분이 반향제거기의 성능을 순간적으로 악화 시키게 된다. 제안된 방법은 두개의 계수세트 들로부터 타이밍 지터 발생시 필요한 계수를 디콘볼루션 알고리듬을 이용하여 FIR 필터링을 통해 구하며 발생하는 지터 성분 의 대부분을 보상 해 준다. 또한 제안 방법은 waveform driven 반향제거기에 비해 약간의 성능열화가 있지만 적은 연산량으로 타이밍 지터보상을 할 수 있는 장점이 있다.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.3
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• pp.417-422
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• 2021

In this paper, a ZQ calibration using a time domain comparator is proposed. The proposed comparator is designed based on VCO, and an additional clock generator is used to reduce power consumption. By using the proposed comparator, the reference voltage and the PAD voltage were compared with a low 1 LSB voltage, so that the additional offset cancelation process could be omitted. The proposed time domain comparator-based ZQ calibration circuit was designed with a 65nm CMOS process with 1.05V and 0.5V supply voltages. The proposed clock generator reduces power consumption by 37% compared to a single time domain comparator, and the proposed ZQ calibration increases the mask margin by up to 67.4%.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.7
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• pp.273-281
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• 2003

This paper proposes a new time synchronization scheme for the Automatic Identification System(AIS). The proposed scheme utilizes a Temperature Compensated Crystal Oscillator(TCXO) as a local reference clock, and consists of a Digitally Controlled Oscillator(DCO), a divider, a phase comparator, and register blocks. Primary time reference is IPPS from GPS receiver that is synchronized to Universal Time Coordinated(UTC). And if GPS is unavailable, other station's signal is utilized as secondary time reference. The phase comparator measures time difference between the 1PPS and the generated transmit clock. The measured time difference is compensated by controlling the DCO and the transmit clock is synchronized to the Universal Time Coordinated(UTC). The synchronized transmit clock(9600Hz) is divided into the transmitting time slot(37.5Hz). The proposed scheme is tested in an experimental AIS transponder set. The experimental result shows that the proposed module satisfies the timing specification of the AIS technical standard, ITU-R M.1371-1.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.12
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• pp.1097-1104
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• 2016

The infrared camera is difficult to satisfy the RE-102 specification of Mil-Std-461. Especially, in the case of UAV electronics, shielded cable is not used, so it is difficult to meet the electromagnetic compatibility standard. In the RE-102 test of the IR camera for UAV, radiated noise exceeding 30 dBuV/m was observed in the range of 50 MHz to 200 MHz. As a result of pcb em scan, peak noise which caused by the harmonic frequency of the digital control signal clock was observed. Radiated noise was reduced by up to 22.9 dBuV/m by applying the spread spectrum clock generator(SSCG) with 3 % down spreading method to the camera control clock.

• Bulletin of the Korean Space Science Society
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• 2010.04a
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• pp.25.2-25.2
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• 2010

MIRIS는 과학기술위성 3호의 주 탑제체로 우주 및 지구의 적외선 관측을 위한 두 개의 카메라 시스템을 가지고 있으며 이를 위한 적외선 검출용 이미지 센서가 각각 장착되어 있다. 이미지 센서를 통해 검출된 이미지 데이터를 읽기 위해 고속의 데이터 처리가 요구되어 FPGA 구성방식으로 전용 제어기를 구성하였다. 우주 및 지구의 적외선 관측용 이미지 센서는 구성 및 동작방법이 달라 요구기능을 만족하는 각각의 전용 이미지 센서 제어기를 개발했다. FPGA를 이용한 이미지 센서 제어기에는 검출된 이미지를 읽기위한 센서 제어 신호발생기, 아날로그 이미지 신호를 디지털 정보로 변환하는 ADC 제어용 신호 발생기, ADC의 출력 신호를 고속의 직렬 통신선로로 출력 하는 기능 외에 동작 모드 및 동작 상태 입력용 DSP 인터페이스, 고속의 직렬 통신 선로에 MIRIS 상태정보 삽입 기능, 제어기의 기능을 원격지에서 확인 할 수 있는 이미지 패턴 생성기능 등을 가지고 있다. 특히, 이미지를 읽기 위한 동작 시에만 클록 주파수를 인가하는 방법으로 FPGA 내부 회로를 구성하여 전류의 소모량을 최소화 하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.11a
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• pp.257-262
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• 1998

본 논문에서는 DSP(Digital Signal Processor)를 이용해 INMARSAT-M 위성통신용 단말기 중의 변ㆍ복조부를 설계하였다. R-RC(ROOt Raised Cosine) 필터에 의해 대역제한된 OQPSK 파형의 발생과 디지털 정합필터(Matched filter)를 이용한 OQPSK 복조, 부호율 1/2이고 구속장이 7인 길쌈부호기 및 클록 복구(Clock recovery)의 구현 알고리즘을 C언어와 어셈블리어로 작성하고, 모뎀을 실제 제작하여 변조기능, 복조기능으로 나누어서 동작 특성을 살펴보았다.

• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.10-15
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• 2006

In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4x oversampling phase and frequency detector structure without a reference clock is described. The phase detector (PD) and frequency detector (FD)are designed by 4X oversampling method. The PD, which uses bang-bang method, finds the phase error by generating four up/down signal and the FD, which uses the rotational method, finds the frequency error by generating up/down signal made by the PD output. And the six signals of the PD and the FD control an amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. Proposed circuit is designed using the 0.18um CMOS technology and operating voltage is 1.8V. With a 4X oversampling PD and FD technique, tracking range of 24% at 3.125Gbps is achieved.