• Journal of IKEEE
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• v.17 no.4
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• pp.544-549
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• 2013

This paper describes a modified binary phase detector (Bang-Bang phase detector - BBPD) for jitter reduction in clock and data recovery (CDR) circuits. The proposed PD reduces ripples in the VCO control voltage resulting in reduced jitter for CDR circuits. A 2.5 Gbps CDR circuit with a proposed BBPD has been designed and verified using Dongbu $0.13{\mu}m$ CMOS technology. Simulation shows the CDR with proposed PD recovers data with peak-to-peak jitter of 10.96ps, rms jitter of 0.86ps, and consumes 16.9mW.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.5
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• pp.777-786
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• 2001

In this paper, as one of countermeasure techniques for a frequency selective fading, a digital slope equalizer(DSE) for 64-QAM digital radio relay system is analyzed in terms of principle, channel modeling, and digital implementation. Also computer simulations have been performed for DSE with a complex 13-tap adaptive time domain equalizer chip. It is shown that about 4.5 dB improvement in system signature can be obtained at the channel edge, and a variety of simulated results are reviewed in view of DSE modeling limit, operating frequency, control coefficient, signal constellation, and system signature. Finally, the functions of DSE chip confirmed up to 61 MHz clock operation are illustrated.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1A
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• pp.27-33
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• 2000

Gardner’s algorithm is one of the useful algorithm for NDD(Non-Decision Directed) symbol synchronization in PAM communications. But the algorithm has a weak point such as pattern noises increasing in multi-level PAM. To insert a pre-filter in the algorithm is able to reduce timing jitter and pattern noise. In this paper, we analyze statistical properties of NDD algorithm to find an optimal parameter of the pre-filter for improving timing jitter and PLL locking. As a simulation result, optimum value of pre-filter parameter, $\beta$, is 0.3 and 0.5 at the roll off factor of the channel, $\alpha$, is 0.5 and 1.0, respectively. Optimum parameters of the pre-filter for clock synchronization of all-digital 256-QAM demodulator is shown in the results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.841-844
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• 2013

This paper suggests methods to drive motor and dsPIC30F2010 microprocessor software design for the Wheel Hub Motor that is incorporated into a hub of the wheel and drives it directly. The minimum function of dsPIC30F2010, system clock, PWM, I/O, communication, applicable to hub motor control are explained and tested. The algorithm including PI control method was implemented to the system by using dsPIC30F2010 microprocessor functions.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.3
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• pp.14-21
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• 1989

In the digital transmission equipment, the input jitter tolerance is a function of input timing recovery circuit characteristics. Especially, in the asynchronous multiplexers, it is also a function of the frame format, the buffer sizes in the synchronizer and desynchronizer, the PLL transfer function, and operating range of VCO in PLL In this paper, a new algorithm for calculating the jitter tolerance of the saynchronous digital transmission equipment is presented. With the new algorithm, we analyzed how the above factors limit the jitter tolerance in the equipment. We also measured the input jitter tolerance for a 45M-140M multiplexing equipment, whose results show the same trend with calculated tolerance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4C
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• pp.342-349
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• 2008

This paper presents a new digit-serial systolic multiplier over $CF(2^m)$ for cryptographic applications. When input data come in continuously, the proposed array produces multiplication results at a rate of one every ${\lceil}m/D{\rceil}$ clock cycles, where D is the selected digit size. Since the inner structure of the proposed array is tree-type, critical path increases logarithmically proportional to D. Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to D. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementations.

• Journal of IKEEE
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• v.23 no.2
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• pp.461-468
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• 2019

A continuous-time Delta-Sigma ADC has various benefits; it does not require an explicit anti-aliasing filter, and it is able to handle wider-band signals with less power consumption in comparison with a discrete-time Delta-Sigma ADC. However, it inherently needs to sample the signal with a high-speed clock, necessitating a complex decimation filter that operates at high speed in order to convert the modulator output to a low-rate high-resolution digital signals without causing aliasing. This paper proposes a continuous-time Delta-Sigma ADC architecture that employs pulse-width modulation and shows that the proposed architecture lends itself to a simpler implementation of the decimation filter using a lookup table.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.55-62
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• 2000

This paper presents an analysis of the chaotic behavior in the discrete-time voltage mode chaotic generator fabricated using 0.8${\mu}{\textrm}{m}$ single poly CMOS technology. An approximated empirical equation is extracted from the measurement data of a nonlinear function block. Then the bifurcation diagram is simulated according to input variables and Lyapunov exponent λ which represent a dependence on an initial value is calculated. We show the interrelations among time waveforms, state transition, and power spectra for the state condition of chaotic circuit, such as equilibrium, periodic, and chaotic state. And results of experiments in the chaotic circuit with the $\pm$2.5V power supply and sampling clock frequency of 10KHz are shown and compared with the simulated results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.1941-1948
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• 1997

In this paper, the power efficient linear upconversion mixer which is a functional circuit in transmit path of intermediate frequency(IF) part of Code Division Multiple (CDMA) cellular phone was explained. In generally, the low CMOS devices limits the implementation of upconversion mixer especially for lower loads. Using replica transconductor, the linear range is extended up to the limit. Thiscircuit was imprlemented using $0.8{\mu}\textrm{m}$ N-well CMOS technology with 2-poly/2-metal. The active area of chip is $0.53mm{\times}0.92mm$. The power consumption is 30mW with 3.3V suply voltage. The 1dB conpression characteristics is -27.3dB with $25{\Omega}$. load and being applied by 2-tone input signal. The mixer operates properly above 200MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.19-27
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• 2002

Characteristics of interconnect lines considering underlayer geometries of a silicon substrate and crossing metal lines are experimentally analyzed through elaborately devised patterns. In this work, test patterns for transmission lines having several kinds of underlayer geometries were devised, and the signal characteristics and responses are measured by S-parameter and time domain reflection meter (TDR). The patterns were designed and fabricated with a deep-submicron CMOS DRAM technology having 1 Tungsten and 2 Aluminum metals. From the analysis of measured results on the patterns, it is founded that the effects of underlayter line structures on line parameters (especially line capacitance and resistance) and signal distortions occurred from them cannot be negligible. The results provide useful and insightful understanding in the skew balance of package leads and global signal lines such as high-speed clock and data lines.