• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.1
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• pp.9-18
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• 2008

Recently according to the development of an information society the information technology equipments which a clock frequency has the facility over a number giga hertz have been developed much. And we have research which leakage electromagnetic signals can use at the communication security and tapping. In this paper, we restored leakage electromagnetic signals of the monitors. And we proposed efficient recovery technique to restore the screen of the monitor. First of all, we understand a screen characteristic of the monitor. And then we restored a monitor screen from leakage electromagnetic signals from the monitor. For also we tried to use a Wavelet transform and filters to remove the noise for better performance. In the result of the experiment, we used leakage electromagnetic signals and confirmed the possibility of a monitor screen of the recovery. And we improve the performance with Wavelet transform and filters.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.1
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• pp.85-91
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• 2012

In this paper, we implemented a Ka-band frequency synthesizer for millimeter wave seeker. we designed for high frequency resolution and frequency hopping response time in the digital synthesis method which uses DDS(Direct Digital Synthesizer). but frequency bandwidth was limited low frequency because DDS output frequency was limited 1/2 by system clock. thus, frequency synthesizer was converted to Ka-band using the frequency multiplier ${\times}4$ and local oscillator. proposed frequency synthesizer was bandwidth 500MHz, frequency switching time was $0.7{\mu}s$, spurious level was suppressed below -52dBc. phase noise was -99dBc/Hz at offset 100kHz and flatness was ${\pm}1dB$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.5
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• pp.1103-1108
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• 2010

In this paper, Frequency Synthesizer which is widely used for FH-SS system is proposed and the experimental results are analyzed. The performance of the DPLL(Digital Phase-Locked-Loop), which is the main part of the Synthesizer is analyzed by the computer program. Using Maxplus-II tool provided by altera. co., ltd, each part of the DPLL is designed and all of them is integrated into EPM7064SLC44-10 chip. And the simulation results are compared with the characteristics of the implemented circuits for analysis. And the experiential results show that the N value of the loop filter is toggled to adjacent N value, which result in phase jitter of the output. It can be resolved by increasing DCO(Digital Controlled oscillator) clock rate.

• Proceedings of the Korean Society for Agricultural Machinery Conference
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• 2017.04a
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• pp.165-165
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• 2017

모돈은 사육 특성상 제한된 파일롯 공간 안에 장시간 머물기 때문에 과중한 몸무게에 의한 지제 이상, 섭식 등의 불량, 수면상태의 불량 등을 지속적으로 관찰해야 하는 대상이다. 측면에 다수의 초음파 센서를 설치하여 기립의 상태 및 운동 시 몸체 궤적의 특성을 분석하여 종합적으로 모돈의 행동 특성을 정량화 하고자 하였다. 이 과정에서 계측 신호의 값을 대수적으로 비교하는 방식에 한계가 있음을 발견하였고, 이를 해결하고자 10 Hz/Ch 내외의 시계열 상대거리 궤적 신호를 주파수 도메인으로 변경하여 분석을 수행하였다. 일정 주파수에 집중되어 있는 주파수 값의 크기 변화(파워 스펙트럼 밀도)를 기준으로 모돈의 움직임의 정상 상태 유무 판별이 가능하였다. 단, 이러한 분석은 계측 데이터를 일괄 처리 방식으로 분석하는 방법으로 도출이 되었으므로, 계측과 정량 분석을 동시에 수행하기 위한 개선이 필요하였다. 계측 시스템에서 사용한 마이크로 프로세서는 Nucleo-446(STMelectronics, CA, USA)로 180 Mhz의 클럭 속도로 작동하나, 총 100 Hz 내외의 16비트 계측 신호에 대해 추가적으로 FFT 등의 주파수 변환 신호 처리를 수행하기에는 연산 능력이 부족하였다. 한편, 주파수 분석의 주기를 1분 단위로 할 경우 처리해야할 정보의 크기는 $100{\times}60{\times}5{\times}2Byte$ 이므로 1분 내에 해당 연산을 종료할 수 있는 추가의 연산 장치가 필요하였다. 계측과 주파수 도메인 변환 연산을 동시에 수행하기 위하여 1 Ghz의 연산능력을 가진 ARM A9 계열의 초소형 멀티코어 AP인 NanoPi Neo Air(Friendlyarm, Guangzhou, China)을 선정하였다. 4개의 코어를 각각 계측, Median 필터링, Smoothing 연산, FFT 분석에 사용하여 1분 단위, 2분 단위, 5분 단위의 주파수 분석을 동시에 수행하였다. 병렬 연산 라이브러리는 오픈 소스인 MPICH(www.mpich.org)를 이용하였다. 상대적으로 여유있는 자원을 보유하고 코어를 실시간으로 결정하여 다수의 모돈 개체 동시 모니터링을 위한 네트워크 연결 역할을 동시에 수행하도록 하였다. 1주일 내외의 요인 실험 수행 결과, 약 70 Mbyte의 데이터가 축적이 되었으며, 1분 단위, 2분 단위, 5분 단위의 주파수 도메인 변환 후 결과를 동시에 취득할 수 있었다. 일부 주파수 도메인 상의 파워 밀도 값이 모돈의 행동 특성에 분석에 유효한 정보를 제공함을 발견하였다. 모돈사 내 현장 보급이 가능한 초소형 AP와 멀티 코어 기반 병렬 처리 기법을 이용한 현장 진단 시스템 개발 연구를 지속적으로 수행할 것이다.

• Korean Journal of Optics and Photonics
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• v.13 no.4
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• pp.295-300
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• 2002

We developed an optical transmitter and receiver for an electrical time division multiplexed (ETDM) 20 Gb/s optical transmission system, and experimentally investigated their characteristics. Especially, the clock extraction circuit, which is a key component in realizing broadband optical transmission receivers, was realized by using an NRZ-to-PRZ converter implemented with a half-period delay line and an EX-OR, a high-Q bandpass filter using a cylindrical dielectric resonator, and a microstrip coupled-line bandpass filter. Finally, the bit-error-rate of demultiplexed 10 Gb/s electrical signal after back to-back transmission was measured, and a high receiver sensitivity [-26.2 dBm for NRZ ($2^{7}-1$) pseudorandom binary sequence (PRBS)] was obtained

• The KIPS Transactions:PartA
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• v.15A no.3
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• pp.161-166
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• 2008

In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field GF($2^m$) using the polynomial basis representation. The proposed systolic array is based on the most significant digit first (MSD-first) multiplication algorithm and produces multiplication results at a rate of one every "m/D" clock cycles, where D is the selected digit size. Since the inner structure of the proposed multiplier is tree-type, critical path increases logarithmically proportional to D. Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to D. Furthermore, since the new architecture has the features of a high regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation.

• Journal of the Korean Institute of Intelligent Systems
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• v.22 no.1
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• pp.49-55
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• 2012

Asynchronous counters, where the counter value is changed not by a synchronizing clock but by outer inputs, are used in various modern digital systems such as spaceborne electronics. In this paper, we propose a scheme of fault tolerance for asynchronous counters with critical races caused by total ionizing dose (TID) in space. As a typical design flaw of asynchronous digital circuits, critical races cause an asynchronous circuit to show non-deterministic behavior, i.e., the next stable state of a state transition is not a fixed value but may be any value of a state set. Using the corrective control scheme for asynchronous sequential machines, this paper provides an existence condition and design procedure for a state feedback controller that can invalidate the effect of critical races. We implement the proposed control system in VHDL code and conduct experiments to demonstrate that the proposed control system can overcome critical races.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.281-286
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• 2002

In this paper we, implement LSB-first digit-serial systolic multiplier for computing modular multiplication $A({\times})B$mod G ({\times})in finite fields GF $(2^m)$. If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of regularity, modularity, and unidirectional data flow, it shows good extension characteristics with respect to m and L.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.600-603
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• 2008

In this paper, a new circuit design named memory-in-pixel for low power consumption of the liquid crystal display (LCD) is presented. Since each pixel has a memory, it is able to express 8 color grades using the data saved in the memory without the operation of the gate and source driver ICs so that it can reduce the power consumption of the LCD panel. A memory circuit consists of modified S-R flip-flop (NAND-type) implemented in the pixel, which can supply AC bias for operating the liquid crystal (LC) with the interlocking clocks (CLK_A and CLK_B). This circuit is more complex than the inverter-type memory circuit, but it has lower power consumption of approximately 50% than the circuit. We have investigated the power consumption both NAND and inverter-type memory circuit using a Smart SPICE for the resolution of $96{\times}128$. The estimated power consumption of the inverter-type memory was about 0.037mW. On the other hand, the NAND-type memory showed power consumption of about 0.007mW.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.8
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• pp.863-870
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• 2003

The digital transmission system entered in a RF region as digital system use IC chips of the speeder edge rate and clock speed nowadays. Optical path really was used in order to obtain the more capacity. In this paper, we described importance of electrical interconnect to get the signal integrity in optical module by simulation and experiment. 12 channel${\times}$2.5 G/ps optical parallel transmitter modules were manufactured by two different method ; access lines with microstrip and stripline type. We have clearly shown that the optical module adopting microstrip type with S$\sub$11/ $\geq$ -10 dB presents distortion but the optical module adopting stripline type with S$\sub$11/ $\leq$ : 15 dB obtains eye opening in 2.5 Gbis optical eye pattern response.