• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.17-24
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• 2004

This paper describes a novel bit line structure to minimize coupling noise induced by coupling capacitance between bit lines. In DRAMs coupling capacitance is inherently present bit lines. As in submicron process the bit line space gets narrower. bit line coupling capacitance increases and this increased coupling capacitance sharply raises cross-talk noise. In this paper using different layers of metal for adjacent bit lines has been tested to reduces cross-talk noise and a novel bit line structure capable of reducing capacitance is introduced and verified.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.12
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• pp.680-686
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• 2002

In deep-submicron (BSM) design, coupling effects between wires on the bus cause serious problems such as crosstalk delay, noise, and power consumption. Most of the previous works on bus encoding are targeted either to minimize tile power consumption on bus or to minimize the crosstalk delay, but not both. In this paper, we propose a new bus encoding algorithm that minimizes the power consumption on bus and eliminates the crosstalk delay simultaneously. We formulate and solve the problem by minimizing a weighted sum of the self transition and cross-coupled transition activities on bus From experiments using a set of benchmark designs. it is shown that the proposed encoding technique consumes at least 15% less power over the existing techniques, while completely eliminating the crosstalk delay.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.3
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• pp.361-366
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• 2012

This paper proposes a low power capacitor cross-coupled 5.2 GHz band low noise amplifier(LNA) using the current-reused topology with the TSMC 0.18 ${\mu}m$ CMOS process. The proposed 5.2 GHz band LNA uses a capacitor cross-coupled $g_m$-boosting method for reducing current flow of circuit and a current-reused topology to decrease total power dissipation. The parallel LC networks are used to reduce size of spiral inductors. The simulation results show high gain of 17.4 dB and noise figure(NF) of 2.7 dB for 5.2 GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1032-1039
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• 2022

In this paper, we designed and implemented a cavity bandpass filter combined with a cross-coupling equalizer structure to enhance Group delay for 5G mobile network repeater, which can replace the SAW (Surface Acoustic Wave) type bandwidth filter used in the existing mobile communication system. Using the 3D EM simulation tool (HFSS), the resonance frequency, the coupling coefficient between resonators, and external quality coefficient between resonators were calculated. Based on this, a 12th bandpass filter was constructed to have attenuation characteristics of more than 20dB at the edge end of both sides of the band with a metal cavity structure with a frequency band of 3500MHz to 3600MHz and bandwidth of 97.85MHz. The designed bandpass filter satisfies the group delay time requirement for the 5G mobile communication standard and the in-band and out-band frequency responses.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2351-2353
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• 1998

This paper suggests the wheel controller for PWS(Power Wheeled Steering) mobile robot. The proposed controller consists of two parts. To control each motor, the sliding mode controller implemented. This method has robustness about modeling error and disturbance, so the velocity tracking is well guaranteed in the presence of varying load. The design of a fuzzy cross-coupling controller for a PWS mobile robot is described here. Fuzzy cross-coupling control directly minimizes the tracking error by coordinating the motion of the two drive wheels. The fuzzy cross-coupling controller has excellent disturbance rejection and therefore is advantageous when the robot is not loaded symmetrically. The capability of the proposed controller was verified through the computer simulation.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.144-151
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• 2022

In this paper, a 1.5V 256kb eFlash memory IP with low area DC-DC converter is designed for battery application. Therefore, in this paper, 5V NMOS precharging transistor is used instead of cross-coupled 5V NMOS transistor, which is a circuit that precharges the voltage of the pumping node to VIN voltage in the unit charge pump circuit for the design of a low-area DC-DC converter. A 5V cross-coupled PMOS transistor is used as a transistor that transfers the boosted voltage to the VOUT node. In addition, the gate node of the 5V NMOS precharging transistor is made to swing between VIN voltage and VIN+VDD voltage using a boost-clock generator. Furthermore, to swing the clock signal, which is one node of the pumping capacitor, to full VDD during a small ring oscillation period in the multi-stage charge pump circuit, a local inverter is added to each unit charge pump circuit. And when exiting from erase mode and program mode and staying at stand-by state, HV NMOS transistor is used to precharge to VDD voltage instead of using a circuit that precharges the boosted voltage to VDD voltage. Since the proposed circuit is applied to the DC-DC converter circuit, the layout area of the 256kb eFLASH memory IP is reduced by about 6.5% compared to the case of using the conventional DC-DC converter circuit.