• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.7-16
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• 2000

This paper reports a methodology and its application for extracting cell capacitances and parasitic capacitances in a stacked DRAM cell structure by a numerical technique. To calculate the cell and parasitic capacitances, we employed finite element method (FEM), The three-dimensional DRAM cell structure is generated by solid modeling based on two-dimensional mask layout and transfer data. To obtain transfer data for generating three-dimensional simulation structure, topography simulation is performed. In this calculation, an exemplary structure comprising 4 cell capacitors with a dimension of $2.25{\times}1.75{\times}3.45{\mu}m^3$, 70,078 nodes with 395,064 tetrahedra were used in ULTRA SPARC 10 workstation. The total CPU time for the simulation was about 25 minutes, while the memory size of 201MB was required. The calculated cell capacitance is 24.34fF per cell, and the influential parasitic capacitances in a stacked DRAM cell are investigated.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3136-3138
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• 2000

마이크로머시닝을 이용한 각속도 센서에서는 기계 구조체의 기준진동에 의한 캐패시턴스의 변화와 인가되는 각속도에 따른 캐패시턴스의 변화를 감지하야 한다. 이러한 캐패시턴스의 변화량을 전기적으로 감지하는데 있어서 기준진동을 위해 구조체에 인가되는 구동신호의 간섭이 최소화 되도록 구조체를 설계하여야 하고 회로적으로 간섭을 상쇄할 수 있어야 미소한 캐패시턴스의 변화량을 감지하여 각속도 센서의 감도를 극대화할 수 있다. 본 논문에서는 이러한 구동신호의 간섭을 상쇄하여 미소캐패시턴스 변화를 감지하는 회로를 설계 하였다.

• Journal of the Korean Electrochemical Society
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• v.6 no.4
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• pp.255-260
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• 2003

The complex capacitance analysis was performed in order to examine the potential-dependent EDLC characteristics of porous carbon electrodes. The imaginary capacitance profiles $(C_{im}\;vs.\;log\lf)$ were theoretically derived for a cylindrical pore and further extended to multiple pore systems. Two important electrochemical parameters in EDLC can be estimated from the peak-shaped imaginary capacitance plots: total capacitance from the peak area and $\alpha_0$ from the peak position. Using this method, the variation of capacitance and ion conductivity in pores can be traced as a function of electric potential. The electrochemical impedance spectroscopy was recorded on the mesoporous carbon electrode as a function of electric potential and analyzed by complex capacitance method. The capacitance values obtained from the peak area showed a maximum at 0.3V (vs. SCE), which was in accordance with cyclic voltammetry result. The ionic conductivity in pores calculated from the peak position showed a maximum at 0.2 V (vs. SCE), then decreased with an increase in potential. This behavior seems due to the enhanced electrostatic interaction between ion and surface charge that becomes enriched at more positive potentials.

• Journal of the Korean Electrochemical Society
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• v.13 no.4
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• pp.223-234
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• 2010

In this review, the theory and applications of the complex capacitance analysis, which can be utilized in analyzing capacitor-like electrochemical systems, were summarized. Theoretically, it was suggested that the imaginary capacitance plots (Cim vs. log f) can provide a simple way to analyze electrochemical characteristics of capacitive systems, without complicated mathematical calculations. The usefulness of the complex capacitance analysis has been demonstrated by applying it to analyze EDLC characteristics of practical porous carbon electrodes, ionic conductivities inside small pores, and ionic resistances in the catalyst layers of polymer electrolyte membrane fuel cells.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.7-12
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• 2004

An improved extraction method considering ac current crowding effect is investigated to determine intrinsic ( $C_{\mu}$) and extrinsic ( $C_{\mu}$) base-collector capacitances of bipolar junction transistors separately. The drawbacks of conventional methods are pointed out, and the improved extraction equations are derived from a cutoff mode equivalent circuit with the ac crowding capacitance. The frequency response curves of modeled current and power gains using the extracted values of $C_{\mu}$ and $C_{\mu}$ have much better agreements with measured ones than those of the conventional methods, verifying the accuracy of the improved technique.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.62-66
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• 2011

In this study, a new RF method to extract the drain-source voltage Vds-dependent gate-bulk capacitance of deep-submicron MOSFETs is developed by determining Vds-independent gate-source overlap capacitance using measured S-parameters. The accuracy of extraction method is verified by observing good agreements between the measured and modeled S-parameters. The lateral channel doping profile in the drain region is experimentally measured using a Vds-dependent curve of the overlap and depletion length obtained from the extracted data.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.44-53
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• 1999

This paper are reported a methodology and application for extracting parasitic capacitances in a multi-level interconnect semiconductor structure by a numerical technique. To calculate the parasitic capacitances between the interconnect lines, we employed finite element method (FEM) and calculated the distrubution of electric potential in the inter-metal layer dielecric(ILD) by solving the Laplace equation. The three-dimensional multi-level interconnect structure is generated directly from two-dimensional mask layout data by specifying process sequences and dimension. An exemplary structure comprising two metal lines with a dimension of 8.0$\times$8.0$\times$5.0$\mu\textrm{m}^3/TEX>, which is embedded in three dielectric layer, was simulated to extract the parasitic capacitances. In this calculation, 1960 nodes with 8892 tetrahedra were used in ULTRA SPARC 1 workstation. The total CPU time for the simulation was 28 seconds, while the memory size of 4.4MB was required.

• Progress in Medical Physics
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• v.3 no.2
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• pp.43-57
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• 1992

Phase detector techique provides a unique probe to membrane recycling phenomenon by enabling dynamic monitoring of cell membrane capacitance. However, it has inherent errors due to constant changes in measurement environments. The present study analyzed several error sources to develope application criteria of this technique. and the following was found based on a theoretical analysis. The initial phase angle has to be appropriately selected to minimize the error due to perturbation of access and membrane conductances. Excitation frequency is also important to determine the initial phase angle. However. deviation of the phase angle from a predetermined initial value during the measurement period does not affect capacitance estimation to a significant degree. Despite an appropriate initial phase selection an error in scaling factor is expected for a large increase in capacitance during exocytosis. which may be overcome by iteratively correcting the scaling factor over the measurement period. These results will provide a useful guideline in practical application of this technique.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1530-1532
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• 2002

전력선 통신 시스템을 간략히 살펴보면 송전단과 수전단으로 나누어 볼 수 있다. 송전단은 전력을 송전하기 위한 설비와 신호를 싣고 분리하는 결합회로로 구성되며 수전단은 수전설비와 결합회로로 분리된다. 결합회로는 $BaTiO_3$를 주성분으로 하는 고유전율 및 대용량의 캐패시터로 구성되었다. 이 캐패시터를 변압기 외부에 사용하므로, 직사광선에 의한 온도 변화가 생길 것이며 이 변화에 따라 캐패시턴스 값의 변화가 생길 것이므로 HPF로 사용할 때 캐패시턴스 값의 변화로 주파수에 영향을 줄 것이다. 주위온도에 따른 캐패시턴스의 변화가 HPF의 동작에 어떠한 영향을 미치는지 고찰하고자한다. 이에 본 연구에서는 수전단의 10KV이하 배전 선로에 사용되는 Coupling Capacitor의 외부온도를 변화시켜 전기적 특성의 변화를 고찰함으로서, HPF로서의 사용될수 있는지 확인하고자 한다.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.276-277
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• 2017

전력변환장치에 널리 사용되는 전해 캐패시터는 그 수명이 상대적으로 짧은 것으로 알려져 있으며, 전력변환장치의 신뢰성 확보를 위해서는 등가직렬저항 또는 캐패시턴스의 추정을 통해 전해 캐패시터의 열화상태를 진단할 필요가 있다. 본 논문에서는 부스트 컨버터에서 평균 모델 기반 디지털 제어를 통해 전해 캐패시터의 캐패시턴스를 추정하는 방법에 대해 연구를 진행하였고, 시뮬레이션과 실험을 통해 그 특성을 평가하였다.