• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.6
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• pp.876-885
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• 2000

A new and simple method is presented for determining the parasitic resistances of MESFET and HEMT from the measured S-parameters under normal active bias without depending on additional DC measurements or iteration or optimization process. The presented method is based on the fact that the difference between source resistance(Rs) and drain resistance(Rd) can be obtained from the measured Z-parameters under zero bias condition. It is possible to define the new internal device including intrinsic device and 3 parasitic resistances by elimination the parasitic inductances and capacitances from the measured S-parameters. Three parasitic resistances are calculated easily from the fact that the real parts of Yint,11 and Yint,12 of intrinsic Y-parameters are zero theoretically and the relations between S-,Z-, Y-matrices. The calculated parasitic resistances using the presented method and successively calculated equivalent circuit parameters give modeled S-parameters which are in good agreement with the measured S-parameters up to 400Hz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.2 s.117
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• pp.177-182
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• 2007

This paper presents the InGaP/GaAs HBT differential LC VCO with low phase noise performance for adaptive feedback interference cancellation system(AF-lCS). The VCO is verified with enhanced tank structure including filtering technique. The output tuning range for proposed VCO using asymmetric inductor and symmetric capacitors withlow pass filtering technique is 207 MHz. The output powers are -6.68 including balun and cable loss. The phase noise of this VCO at 10 kHz, 100 kHz and 1 MHz are -102.02 dBc/Hz, -112.04 dBc/Hz and -130.40 dBc/Hz. The VCO is designed within total size of $0.9{\times}0.9mm^2$.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.2
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• pp.47-54
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• 1990

In this paper, we design the 4-bit phase shifter which have $22.5^{\circ},45^{\circ},90^{\circ}$ and $180^{\circ}$ phase shift by applying the loaded line and switched network phase shifter. Its phase shift is variable with changing of the stub and passive device parameters. The experiments show the 6.5 dB average insertion loss and $10^{\circ}$ average phase error at center frequency, 6GHz. The results of experiment agree well with the theories except $180^{\circ}$ phase shifter.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.14 no.6
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• pp.117-124
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• 2015

In this paper, a new kind of wideband, low-loss composite right/left-handed (CRLH) transmission line (TL) and a Wilkinson power divider are presented. The TL is composed of a parallel meander inductor and a series cutting capacitor based on coplanar waveguide (CPW) structure. The power divider is designed by substituting the CRLH-TL into the conventional transmission line. The experiment results show that the TL has a good agreement with the desired results, exhibiting the return losses under 12 dB from 8.4 GHz to 34.4 GHz. The operating frequencies of the power divider are 12.05 GHz to 13.15 GHz and 16.50 GHz to 19.30 GHz, respectively. The 20 dB bandwidths are 8.9 % and 17.9 %, respectively. Typical experimental measurements are conducted and compared with the simulated results.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.117-127
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• 1994

In this paper, electrical and reliability properties of N$_2$O oxides, grown at the temperature of 95$0^{\circ}C$ and 100$0^{\circ}C$ to 74$\AA$, and 82$\AA$. respectively, using NS12TO gas in a conventional furnace, have been compared with those of pure oxide grown at the temperature of 850 to 84$\AA$ using O$_2$ gas. Initial IS1gT-VS1gT characteristics of N$_2$O oxides were similar to those of pure oxide, and reliability properties of N$_2$O oxides, such as charge trapping, interface state density and leakage current at low electric field under F-N stress, were improved much better than those of pure oxide. But, with increasing capacitor area. TDDB characteristics of N$_2$O oxides were more degraded than those of pure oxide and this degradation of TDDB characteristics was more severe in 100$0^{\circ}C$ N$_2$Ooxide than in 95$0^{\circ}C$ N$_2$O oxide. The improvement of reliability properties excluding TDDB in N$_2$Ooxides was attributed to the hardness of the interface improved by nitrogen pile-up at the interface of Si/SiO$_2$, but on the other hand, the degradation of TDDB characteristics in N$_2$O oxides was obsered due to the increase of local thinning spots caused by excessive nitrogen at interface during the growth of N$_2$O oxides.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.513-519
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• 2001

We proposed Si-rich tungsten silicide (WSix) films for alternate gate electrode of deep-submicron MOSFETs. The investigation of WSix films deposited directly on SiO$_2$ indicated that the annealing of as-deposited films using a rapid thermal processor (RTP) results in low resitivity, as well as negligible fluorine (F) diffusion. Specifically, the resitivity of RTP-annealed samples at 800 $^{\circ}C$ for 3 minutes in vacuum was ~160 $\mu$$\Omega$ . cm, and the irregular growth of an extra SiO$_2$ layer due to F diffusion during annealing has not been observed. In addition, the analysis of the WSix-SiO$_2$-Si (MOS) capacitors exhibits excellent electrical characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.69-75
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• 2004

This work proposes an 8b 220 MS/s 230 mW 3-stage pipeline CMOS ADC with on-chip filers for temperature- and power- insensitive voltage references. The proposed RC low-pass filters improve switching noise performance and reduce reference settling time at heavy R & C loads without conventional off-chip large bypass capacitors. The prototype ABC fabricated in a 0.25 um CMOS occupies the active die area of 2.25 $\textrm{mm}^2$ and shows the measured DNL and INL of maximum 0.43 LSB and 0.82 LSB, respectively. The ADC maintains the SNDR of 43 dB and 41 dB up to the 110 MHz input at 200 MS/s and 220 MS/s, respectively, while the SNDR at the 500 MHz input is degraded as much as only 3 dB than the SNDR at the 110 MHz input.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.10
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• pp.57-62
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• 2009

This study proposes the optimization and numerical analysis of the antenna circuit for antenna design with 13.56 MHz as transmitting wireless power, for calculating the dose radiation exposure to the real time. The 13.56 MHz of the antenna frequency bands is used to the loop antenna which is a induced current for transmitting the power with wireless the reader to the tag. The study compared to the real measurement value as calculating the value of the inductance and capacitance through the numerical analysis for the antenna LC resonance using the theory of the electromagnetic induction method. We tried to search for the resonance point as the voltages of both sides of antenna coil by the scope measures of the peak point, as we tried to be variable the resonance capacitor for the optimization tuning of the antenna circuit and the matching of the antenna port. We convince our research contributes to help the design and application technology of the wireless power transmit system which is received power supply with wireless.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.69-78
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• 2007

A Frequency synthesizer for T-DMB and mobile-DTV applications was designed using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors were chosen for VCO core to reduce phase noise. The VCO range is 920MHz-2100MHz using switchable inductors, capacitors and varactors. Varactor biases that improve varactor acitance characteristics were minimized as two, and $K_{VCO}$(VCO gain) value was aintained by switchable varactor. Additionally, VCO was designed that VCO gain and the interval of VCO gain were maintained using VCO gain compensation logic. VCO, PFD, CP and LF were verified by Cadence Spectre, and divider was simulated using Matlab Simulink, ModelSim and HSPICE. VCO consumes 10mW power, and is 56.3% tuning range. VCO phase noise is -127dBc/Hz at 1MHz offset for 1.58GHz output frequency. Total power consumption of the frequency synthesizer is 18mW, and lock time is about $140{\mu}s$.

• Journal of the Korean Electrochemical Society
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• v.3 no.4
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• pp.241-245
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• 2000

The objective of this work Is to design, fabricate, and characterize pseudo-capacitor using amorphous $MnO_2\;nH_2O$ electrode material. The cyclic voltammogram under 100mV/s scan rate of the material shows the electrochemically stable potential window of 1V and the specific capacitance of 250F/g. The TDMA pulse test result indicates that the TDMA system (2 parallel-pseudo-capacitor systems) has the ohmic voltage drop of 0.22V and the capacitor voltage drop of 0.38V. The total voltage drop of the TDMA system is 0.60V and less than 1V of which value is the maximum voltage drop requirement or the TDMA satellite phone. Also, the TDMA system had the ESR of $55m{\Omega}$ and the capacitance of 105mF. Therefore, it is confirmed that the TDMA system has the application feasibility as load-leveling capacitor for the satellite phone.