• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.59-64
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• 2013

In this paper, a capacitor multiplier with good frequency characteristics has been proposed. Effective capacitance of conventional capacitor multiplier decreases as frequency increases due to internal series resistance. On the other hand, the proposed capacitor multiplier using cascode structure has smaller internal resistance, thus shows good frequency characteristics. Conventional and proposed capacitor multiplier were fabricated using Samsung $0.13{\mu}m$ CMOS process and frequency characteristics of capacitor multipliers were measured using LPF. Measurement results show that the conventional capacitor multiplier has maximum 53% of capacitance error, however the proposed multiplier has less than 10% of capacitance error for the frequency change from 100kHz to 1MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6A
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• pp.697-704
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• 2004

This paper describes the design and fabrication of an MMIC variable gain LNA for 5GHz wireless LAN applications, using 0.5${\mu}{\textrm}{m}$ gate length GaAs MESFET transistors. The advantages of high gain and low noise performance of E-MESFETS and excellent linear performance of D-MESFETS are combined as a cascode topology in this design. Behavioral model equations are derived from the MESFET nonlinear current voltage characteristics by using Turlington's asymptote method in a cascode configuration. Using the behavioral model equations, a 4${\times}$50${\mu}{\textrm}{m}$ E-MESFET as a common source amplifier and a 2${\times}$50${\mu}{\textrm}{m}$ D-MESFET as a common gate amplifier are determined for the cascode amplifier. The fabricated variable gain LNA shows a noise figure of 2.4dB, variable gain range of more than 17dB, IIP3 of -4.8dBm at 4.9GHz, and power consumption of 12.8mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.1
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• pp.9-15
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• 2015

A CMOS band-pass delta-sigma modulator(BPDSM) and cascode class-E power amplifier have been developed CMOS for Class-S power amplifier applications. The BPDSM is operating at 1-GHz sampling frequency, which converts a 250-MHz sinusoidal signal to a pulse-width modulated digital signal without the quantization noise. The BPDSM shows a 25-dB SQNR(Signal to Quantization Noise Ratio) and consumes a power of 24 mW at an 1.2-V supply voltage. The class-E power amplifier exhibits an 18.1 dBm of the maximum output power with a 25% drain efficiency at a 3.3-V supply voltage. The BPDSM and class-E PA were fabricated in the Dongbu's 110-nm CMOS process.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.6
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• pp.127-132
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• 2018

In this paper, a high conversion gain cascode mixer was designed in W-band and verified by the fabrication and measurements. In the high frequency band such as a W-band, the conversion loss of a mixer is increased because of the poor performance of transistors. This high conversion loss of the mixer requires additional circuits which can give an extra gain such as an RF buffer amplifier, and this can affects the linearity and stability of the overall systems. Therefore, it is necessary to maximize the conversion gain of the mixer. To maximize the conversion gain of the mixer, biases of the transistor were optimized, and output load impedance was optimized by the load-pull simulations. The designed mixer was fabricated in $0.1-{\mu}m$ GaAs pHEMT technology and verified by the measurements. The measurement results shows a maximum conversion gain of -4.7 dB at W-band and an input 1-dB compression point of 2.5 dBm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.8
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• pp.966-974
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• 2019

In this study, we propose a CMOS power amplifier (PA) using a bypass technique to enhance the efficiency in the low-power region. For the bypass structure, the common-gate (CG) transistor of the cascode structure of the driver stage is divided in two parallel branches. One of the CG transistors is designed to drive the power stage for high-power mode. The other CG transistor is designed to bypass the power stage for low-power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. The measured maximum output power is 20.35 dBm with a power added efficiency of 12.10%. At a measured output power of 11.52 dBm, the PAE is improved from 1.90% to 7.00% by bypassing the power stage. Based on the measurement results, we verified the functionality of the proposed bypass structure.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.983-986
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• 2000

본 논문에서는 저전압(2V) 동작이 가능하도록 완전차동 구조의 아날로그 능동소자에 전압조절을 위한 튜닝 회로를 추가한 능동소자를 제안하였다. 아날로그 능동소자는 이득특성에 영향을 주는 트랜스컨덕턴스값을 증가시키기 위해 CMOS 상보형 캐스코드 방식을 이용하여 구성되었다. 0.25㎛ CMOS n-well 공정 파라미터를 이용한 HSPICE 시뮬레이션 결과, 제안된 아날로그 능동소자는 비우성극점의 제거로 안정성이 향상되었으며, 2V 공급전압하에서 42dB의 이득값과 200MHz의 단위 이득주파수 특성을 나타내었다. 소비전력값은 0.32mW를 나타내었다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.12
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• pp.2273-2277
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• 2010

In this paper a 2.4GHz CMOS colpitts type microwave oscillator was designed and fabricated using H-spice and Cadence Spetre. There are 140MHz difference between the oscillation frequency and the resonance frequency of a tank circuit of the designed oscillator. The difference is seemed to be due to the parasitic component of the transistor. The inductors used in this design are the spiral inductors proposed in other papers. Cascode current source was used as a bias circuit of a oscillator and the output transistor of the current source is used as the oscillation transistor. A common drain buffer amplifier was used at the output of the oscillator. The measured oscillation frequency and output power of the oscillator are 2.173GHz and -5.53dBm.

• Journal of Korea Multimedia Society
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• v.6 no.1
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• pp.161-166
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• 2003

This paper presents a high gain LNA for a bluetooth application using 0.25$\mu\textrm{m}$ CMOS technology. The conventional one stage LNA has a low power gain. The presented one stage LNA using a cascode inverter LNA with a voltage reference and without a choke inductor has an improved Power gain. Simulation results of the 2.4GHz designed LNA shows a high power gain of 21dB, a noise figure of 2.2dB, and the power consumption of 255mW at 2.5V power supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.93-96
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• 2003

본 논문은 캐스코드 구조에서의 바이어스 조건에 대해 분석하고 이를 이용하여 C-Band용 마이크로파 수신기에서의 자기발진믹서를 분석하였다. 자기발진믹서는 두 개의 FET에 의해서 동작되며 상위 FET는 비교적 높은 Q값을 가지는 유전체공진기에 의해서 발진기로 동작하도록 하였으며, 아래쪽 FET는 믹서로 동작시켰다. 모의실험 결과에 의해 초기 드레인 전압은 $V_{ds}$ =2.5V이고 게이트바이어스 전압은 $V_{gs1}$=-0.2V와 $V_{g2}$=0V로 선정하였다. 선정된 바이어스를 통해 설계된 5.15GHz의 발진기 출력은 5.92dBm, 위상잡음은 -132.0dBc/100KHz, 믹서의 변환손실은 약 -3dB를 얻었다.얻었다.

• Proceedings of the KIEE Conference
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• 2000.07e
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• pp.149-151
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• 2000

본 논문에서는 완전균형 상보형 적분기에서 그 이득과 단위이득 주파수 특성을 향상시킬 수 있는 high-swing cascode 구조를 이용한 새로운 적분기를 설계하였다. 설계된 high-swing cascode 적분기는 $0.25{\mu}m$ n-well CMOS 공정 파라미터를 이용하여 HSPICE 시뮬레이션 하였으면, 그 결과 제안된 회로는 2V 공급전압에서 전력소모는 1.04mW이고 차단주파수는 100MHz를 갖으며 이득은 51dB로서 이 적분기를 이용한 능동필터 설계시 요구조건인 40dB 이상의 이득 값을 만족한다.