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http://dx.doi.org/10.6109/jkiice.2019.23.8.966

A 2.4-GHz CMOS Power Amplifier with a Bypass Structure Using Cascode Driver Stage to Improve Efficiency  

Jang, Joseph (School of Electronic Engineering, Soongsil University)
Yoo, Jinho (School of Electronic Engineering, Soongsil University)
Lee, Milim (School of Electronic Engineering, Soongsil University)
Park, Changkun (School of Electronic Engineering, Soongsil University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.23, no.8, 2019 , pp. 966-974 More about this Journal
Abstract
In this study, we propose a CMOS power amplifier (PA) using a bypass technique to enhance the efficiency in the low-power region. For the bypass structure, the common-gate (CG) transistor of the cascode structure of the driver stage is divided in two parallel branches. One of the CG transistors is designed to drive the power stage for high-power mode. The other CG transistor is designed to bypass the power stage for low-power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. The measured maximum output power is 20.35 dBm with a power added efficiency of 12.10%. At a measured output power of 11.52 dBm, the PAE is improved from 1.90% to 7.00% by bypassing the power stage. Based on the measurement results, we verified the functionality of the proposed bypass structure.
Keywords
Bypass structure; cascode; CMOS power amplifier; driver stage; dual-mode;
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