• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.379-388
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• 1998

In this paper we propose a DMR-II shared-medium access control protocol which was developed for the ATM access network users to support isochronous and non-isochronous traffics simultaneously under the bandwidth sharing environment, and describe its architecture and operation principles. The DMR-II protocol uses the slotted-ring topology, and gives the higher transmission priority to the isochronous traffic than the non-isochronous traffic. To support the isochronous traffic it uses the slot reservation mechanism, and maintains the delay variation of the isochronous traffic beyond the threshold value by using the blocking mechanism whenever the total user traffic overflows the network's bandwidth limitation. for the non-isochronous traffic the DMR-II protocol lets all the nodes to have fair transmission chances by using the reset mechanism based on the window counter scheme.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.7
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• pp.1015-1024
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• 1990

This paper proposes a program counter unit(PCU) on the pipelined architecture of RISC (Reduced Instruction Set Computer) type high performance processors, PCU is used for supplying instruction addresses to memory units(Instruction Cache) efficiently. A RISC processor's PCU has to compute the instruction address within required intervals continnously. So, using the method of self-generated incrementor, is more efficient than the conventional one's using ALU or private adder. The proposed PCU is designed to have the fast +4(Byte Address) operation incrementor that has no carry propagation delay. Design specifications are taken by analyzing the whole data path operation of target processor's default and exceptional mode instructions. CMOS and wired logic circuit technologic are used in PCU for the fast operation which has small layout area and power dissipation. The schematic capture and logic, timing simulation of proposed PCU are performed on Apollo W/S using Mentor Graphics CAD tooks.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.04a
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• pp.491-494
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• 2001

IP 망에서 Qos(Quality of Service)를 보장하기 위하여 요구되는 것이 수락 제어이다. 기존의 수락 제어 메커니즘은 크게 RSVP(Resource Reservation Protocol) 시그널링 방법과 MBAC(Measurement Based Admission Control)로 분류된다. 첫번째 방법의 경우 코어 망에서 각 플로우마다 상태를 유지해야 하는 확장성 문제때문에 적용이 쉽지 않고, 두 번째 방법의 경우 긴 경로를 가진 플로우의 경우 짧은 경로를 가진 플로우에 비해 블록킹 확률이 높아지는 문제점이 있다. 본 논문에서는 IP 코어 망에서 사용자의 QoS 요구사항과 서로 다른 경로상의 플로우간 블록킹 확률의 공평성을 위한 TPED MBAC(Two-Phase Edge-to-Edge Distributed Measurement Based Admission Control) 메커니즘을 제안한다. 이 MBAC 메커니즘은 수락 제어를 Quantitative Provisioning 단계와 Qualitative Provisioning 단계로 나누어 수행하며 프로빙 패킷 전송을 위해 홉 카운터에 기반 한 WRR(Weighted Round-Robin) 스케쥴링을 적용함으로써 각 플로우간의 블록킹 확률의 공평성을 제어할 수 있는 메커니즘이다.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.12
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• pp.724-735
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• 2003

In recent high-performance superscalar processors, the result value of an instruction is predicted to improve instruction-level parallelism by breaking data dependencies. Using those predicted values, instructions are speculatively executed and substantial performance can be gained. It, however, requires additional power consumption due to the frequent access and update of the value prediction table. In this paper, first, the trade-off between the performance improvement and the increased power consumption for value prediction is measured and analyzed. And, in order to reduce additional power consumption without performance loss, the technique of controlling speculative execution with confidence counter and predicting useful instructions is developed. Also, in order to prove the validity, a tool is developed that can simulate processor behavior at cycle-level and measure total energy consumption and power consumption per cycle.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.11
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• pp.34-43
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• 1999

A high-speed image processor (HIP) is implemented for a high-speed multi-function peripheral. HIP has a binarization architecture with unified data path. It has the pixel-by-pixel pipelined processing to minimize size of the external memory. It performs pre-processing such as shading correction, automatic gain control (AGC), and gamma correction, and also drives external CCD or CIS modules. The pre-processed data can be enlarged or reduced. Various binarizatin algorithms can be processed in the unified archiecture. The embedded binarization algorithms are simple thresholding, high pass filtering, dithering, error diffusion, and thershold modulated error diffusion. These binarization algorithms are unified based on th threshold modulated error diffusion. The data path is designed to share the common functional block of the binarization algorithms. The complexity of the controls and the gate counts is greatly reduced with this novel architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.32-38
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• 2009

FTT(Fast Fourier Transform) processor is widely used in OFDM(Orthogonal Frequency Division Multiplesing) system. Because of the increased requirement of mobility and bandwidth in the OFDM system, they need large point FTT processor. Since the size of memory which stores the twiddle factor coefficients are proportional to the N of FFT size, we propose a new method by which we can reduce the size of the coefficient memory. In the proposed method, we exploit a counter and unsigned multiplier to generate the twiddle factor indices. To verify the proposed algorithm, we design TFCGs(Twiddle Factor Coefficient Generator) for 1024pint FFTs with R2SDF(Radix-2 Single-Path Delay Feedback), $R2^3SDF,\;R2^3SDF,\;R2^4SDF$ architectures. The size of ROM is reduced to 1/8N. In the case of $R2^4SDF$ architecture, the area and the power are reduced by 57.9%, 57.5% respectively.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.1861-1864
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• 2003

The objective of this study is to suggest the form rolling technology to produce high precision worm. Rack dies and roll dies are usually used to roll parts with worm teeth. The form roiling processes of worm shaft used as automotive part using the rack dies of counter flow type and the roll dies are considered and simulated by the commercial finite element code, DEFORM-3D. It is also important to determine the initial blank diameter in form rolling because it affects the quality of thread. The calculation method of the initial blank diameter in form rolling is suggested and it is verified by FE-simulation. The experiments using rack dies and roll dies are performed under the same conditions as those of simulation. The results of simulation and experiment in this study show that the from rolling process of worm shaft using the rack dies is decidedly superior to that using rolling dies from the aspect of the surface roughness and the profile of worm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2113-2120
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• 2009

User authentication has been one of the most important part of the network system. OTP(One-Time Password) has been developed and applied to the existing authentication system. OTP makes a different password and abrogates used password each time when user is authenticated by the server. Those systems prevent stolen-key-problems which is caused by using the same key every log-in trial. Yet, OTP still has vulnerabilities. In this paper, an advanced protocol which is using clock-count method to apply a stream cipher algorithm to OTP protocols and to solve problems of existing OTP protocols is proposed.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.6
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• pp.151-158
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• 2019

FLUSH+RELOAD attack exposes the most serious security threat among cache side channel attacks due to its high resolution and low noise. This attack is exploited by a variety of malicious programs that attempt to leak sensitive information. In order to prevent such information leakage, it is necessary to detect FLUSH+RELOAD attack in real time. In this paper, we propose a novel run-time detection technique for FLUSH+RELOAD attack by utilizing PCM (Performance Counter Monitor) of processors. For this, we conducted four kinds of experiments to observe the variation of each counter value of PCM during the execution of the attack. As a result, we found that it is possible to detect the attack by exploiting three kinds of important factors. Then, we constructed a detection algorithm based on the experimental results. Our algorithm utilizes machine learning techniques including a logistic regression and ANN(Artificial Neural Network) to learn from different execution environments. Evaluation shows that the algorithm successfully detects all kinds of attacks with relatively low false rate.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.5
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• pp.116-124
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• 2012

In this paper, we propose an efficient lighting control system design for AVR based LSDM control. This paper, an efficient lighting control system design for LSDM control be design divided as the signal control part for I/O data bus and the timer/counter part for clock signal control according to operating conditions. LSDM control logic be optimization to PORTx and DDRx register by specifying the logical value of each bit for effective control signal processing. And, the LSDM control signal by lighting control program execution of ATmega128 be designed to be LSDM lighting control by control logic operating. In this paper, a proposed lighting control system were measured to power loss rate to proved the power loss reduction about lighting status of LSDM control logic by download the lighting control program to system through serial from host PC. As a measurement result, a proposed lighting control system than the existing lighting control system were proved to be effective to the overall power consumption reduction.