Browse > Article

Measurement and Analysis of Power Dissipation of Value Speculation in Superscalar Processors  

이상정 (순천향대학교 정보기술공학부)
이명근 (㈜다이알로직코리아 기술연구소)
신화정 (한양여자대학 전산정보계열)
Abstract
In recent high-performance superscalar processors, the result value of an instruction is predicted to improve instruction-level parallelism by breaking data dependencies. Using those predicted values, instructions are speculatively executed and substantial performance can be gained. It, however, requires additional power consumption due to the frequent access and update of the value prediction table. In this paper, first, the trade-off between the performance improvement and the increased power consumption for value prediction is measured and analyzed. And, in order to reduce additional power consumption without performance loss, the technique of controlling speculative execution with confidence counter and predicting useful instructions is developed. Also, in order to prove the validity, a tool is developed that can simulate processor behavior at cycle-level and measure total energy consumption and power consumption per cycle.
Keywords
Speculative execution; value prediction; processor power dissipation; superscalar processor;
Citations & Related Records
연도 인용수 순위
  • Reference
1 S.Manne,A.Klauser and D.Grunwald, 'Pipeline Gating: Speculation Control for Energy Reduction,' Proceedings of the 25th International. Symposium on Computer Architecture(ISCA-25), June 1998   DOI
2 D.Grunwald,A.Klauser,S.Manne and A. Pleszkun, 'Confidence Estimation for Speculation Control,' Proceedings of the 25th International Symposium on Computer Architecture (ISCA-25), June 1998   DOI
3 B.Calder, G.Reinman and D.Tullsen, 'Selective Value Prediction,' Proceedings of the 26th International Symposium on Computer Architecture(ISCA-26), May 1999
4 D.Friendly, S.Patel, and Y.Patt, 'Putting the Fill Unit to Work : Dynamic Optimizations for Trace Cache Microprocessors,' Proceedings of the 31st International Symposium on Microarchitecture (MICRO-31), Dec 1998   DOI
5 E.Rotenburg, S.Bennett, and J.Smith, 'A Trace Cache Microarchitecture and Evaluation,' IEEE Transaction on Computers, Vol.48 No.2, Feb. 1999   DOI   ScienceOn
6 S.McFarling, 'Combining Branch Predictors,' Technical Report TN-36, Digital Western Research Laboratory, June 1993
7 T.Yeh and Y.Patt, 'Two-level Adaptive Branch Prediction,' Proceedings of the 24th International Symposium Microarchitecture(MICRO-24), Nov. 1991
8 Sang-Jeong Lee and Pen-Chung Yew, 'On Augmenting Trace Cache for High-Bandwidth Value Prediction,' IEEE Transaction on Computers, Vol.51, No.9, p.1074-1088, Sept. 2002   DOI
9 R.Bhargava and L.John, 'Latency and Energy Aware Value Prediction for High-Frequency Processors,' Proceddings of 16th ACM International Conference on Supercomputing, pp. 45-56, June, 2002   DOI
10 A.KleinOsowski, J.Flynn, N.Meares, and D.Lilja, 'Adapting the SPEC 2000 Benchmark Suite for Simulation-Based Computer Architecture Research,' Workshop on Workload Characterization held in conjunction with International Conference on Computer Design, Sept., 2000
11 Sang-Jeong Lee and Pen-Chung Yew, 'On Table Bandwidth and Its Update Delay for Value Prediction on Wide-Issue ILP Processors,' IEEE Transaction on Computers, Vol.50 No.8, p.847-852, Aug. 2001   DOI
12 D.Burger and T.Austin, The SimpleScalar Tool Set, Version 2.0, Technical Report CS-TR-971342, University of Wisconsin, Madison, June 1997
13 M.Lipasti and J.Shen, 'Exceeding the Limit via Value Prediction,' Proceedings of the 29th International Symposium on Microarchitecture(MICRO29), Dec. 1996   DOI
14 K.Wang and M.Franklin, 'Highly Accurate Data Value Predictions using Hybrid Predictor,' Proceedings of the 30th International Symposium on Microarchitecture(MICRO-30), Dec. 1997   DOI
15 M.Borah, R.Owens and M.Irwin, 'Transistor sizing for low power CMOS Circuits,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15 No.6, 1996   DOI   ScienceOn
16 B.Rychlik, j.Faistl, B.Krug, and LShen, 'Efficacy and Performance Impact of Value Prediction,' Parallel Architectures and Compilation Techniques (PACT98), Paris, Oct. 1998   DOI
17 G. Cai, 'Architectural Level Power/Performance Optimization and Dynamic Power Estimation,' Proceedings of the CoolChips Tutorial, An Industrial Perspective on Low Power Processor Design in conjunction with the 32th Annual International Symposium on Microarchitecture (MICRO-32), 1999
18 Y.Sazeides and J.Smith, 'The Predictability of Data Values,' Proceedings of the 30th International Symposium on Microarchitecture(MICRO30), Dec. 1997   DOI
19 C.Leung, D.Brooks, M. Martonosi, and D.Clark, 'Power-Aware Architecture Studies: Ongoing Work at Princeton,' Proceedings of Power-Driven Microprocessor Design Workshop, June 199
20 S. Ghiasi and D. Grunwald, 'A Comparison of Two Architectural Power Models,' Proceedings of the Workshop on Power-Aware Computer Systems in conjunction with ASPLOS-rx, Nov., 2000