• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.203-211
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• 2013

UHF RFID tag designers usually ndde the chip impedance and read power sensitivity value obtained when a tag chip is mounted on a chip pad. The chip impedance, however, is not able to be supplied by chip manufacturer, since the chip impedance is varied according to tag designs and fabrication processes. Instead, the chip makers mostly supply the chip impedances measured on the bare dies. This study proposes a chip impedance and read power sensitivity evaluation method which requires a few simple auxiliary and some RF measuring equipment. As it is impractical to measure the chip impedance directly at mounted chip terminals, some form test fixture is employed and the effect of the fixture is modeled and de-embeded to determine the chip impedance and the read power sensitivity. Validity and accuracy of the proposed de-embed method are examined by using commercial RFID tag chips as well as a capacitor and a resistor the value of which are known.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.12
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• pp.1148-1157
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• 2013

In a passive UHF RFID system, the impedance matching between tag antenna and chip as well as the protocol parameter settings in a reader plays important role in determination of the maximum read-range. Almost no paper, however, has dealt with the above issues in relation with the maximum read range. In this paper, two known methods (of using the value from data sheets and proprietary RFID tester) and our proposing method in chip impedance evaluation are compared in terms of maximum read range. The read range of tags whose antenna impedance is conjugate matched with the chip impedance obtained from the proposed method is improved maximum 73 % more than that of tags from the other methods.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1692-1693
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• 2011

본 논문에서는 전극칩에서 배양하는 세포의 활동성을 실시간으로 모니터링 하기 위해 AC 함수발생기와 Lock-in-amplifier (SR 830, Stanford Research System)를 이용하여 개발한 LabVIEW(National Instrument)기반 세포 임피던스 측정시스템을 제안하였다. 대장암 세포인 HT-29를 다 채널 전극칩에서 60시간동안 배양하는 동안 LabVIEW기반 세포 임피던스 측정시스템을 이용해서 인가하는 신호의 주파수와 세포의 배양시간에 따른 세포 임피던스 변화를 관찰하였다. 결과 HT-29 세포가 전극에 안착하고 증식하기 때문에 전극의 임피던스가 증가한다는 이전 연구결과와 일치하는 측정결과를 얻었고, 이 결과를 통해서 제안한 LabVIEW 기반 세포 임피던스 측정시스템이 암세포 연구에 적합하고, 앞으로 유용하게 사용될 수 있음을 확인하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.713-715
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• 2012

본 논문은 24GHz 차량 추돌 예방 레이더 시스템-온-칩을 위한 입력 임피던스, 전압이득 및 잡음지수를 자동으로 측정할 수 있는 새로운 형태의 고주파 자체 내부검사(BIST, Built-In Self-Test) 회로를 제안한다. 이러한 BIST 회로는 TSMC $0.13{\mu}m$ 혼성신호/고주파 CMOS 공정 ($f_T/f_{MAX}$=140/120GHz)으로 설계되어 있다. 알고리즘은 LabVIEW로 구현되어 있다. BIST 알고리즘은 입력 임피던스 정합과 출력 직류 전압 측정원리를 이용한다. 본 논문에서 제안하는 방법은 자동으로 쉽게 고주파 회로의 성능변수를 측정할 수 있기 때문에 시스템-온-칩의 저가 성능 검사의 대안이 될 것으로 기대한다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.12
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• pp.1228-1235
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• 2014

Input impedance of UHF RFID tag chip is needed to design a tag. In determining the chip impedance, direct measurement method is adopted commonly. In this paper, problems generated from fixtures that interface between tag chip and coaxial-oriented measurement instrument are investigated and the result of the problems is shown, when the direct measurement method is applied. As an alternative to the method, a modeling method is proposed and its validity and accuracy are shown.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.9-15
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• 2006

This paper shows the impedance profile of PEEC(Partial Equivalent Electrical Circuit) PDN(Power Distribution Networks) including core and I/O circuit. Through the simulated results, we find that the core power noise having connection with I/O power is affected by I/O switching. Also, using designed $74{\times}5inch$ DLL(Delay Locked Loop) test board, we analyzed the effect of power noise on operation region of chip. Jitter of a DLL measure for frequency of $50{\sim}400MHz$ and compared with impedance obtained result of simulation. Jitter of a DLL are increased near about frequency of 100MHz. It is reason that the resonant peak of PDNs has an impedance of more the 1ohm on 100MHz. we present the impedance profile of a chip and board for the decoupling capacitor reduced the target impedance. Therefore, power supply network design should be considered not only decoupling capacitors but also core switching current and I/O switching current.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.61-64
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• 2005

본 연구에서는 $5mm{\times}7mm$ 크기의 적층 세라믹 SMD(surface mounted device)형 PECL VCXO에 테스트지그를 이용하여 스펙트럼을 분석한다. 패키지에 PECL 칩을 장착 후 와이어결선(wire bonding)을 완료한 VCXO는 그 길이 및 패키지 내부의 패턴 등에 의하여 부유인덕턴스(stray inductance) 및 커패시턴스가 발생하고, 칩의 발진부 임피던스에 영향을 준다. 이에 칩이 패키지에 장착된 상태에서 발진부 입력임피던스 영향을 제거하고 안정한 발진기 측정을 통하여 발진기의 정확한 스펙트럼 분석 및 성능을 평가한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.57-57
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• 2001

본 논문에서는 RFID를 위한 읽기 전용 CMOS 트랜스폰더를 one-chip으로 설계하였다. 리더에서 공급되는 자기장으로부터 트랜스폰더 칩의 전원을 공급하기 위한 전파정류기를 NMOS 트랜지스터를 사용하여 설계하였으며, 데이터 저장 소자로는 64비트의 ROM을 사용하였다. 메모리에 저장되어 있는 ID 코드는 Manchester 코딩되어 front-end 임피던스 변조 방식으로 리더에 전송된다. 임피던스 변조를 위한 감폭회로로는 리더와 트랜스폰더 사이의 거리가 변해도 일정한 감폭율을 갖는 새로운 감폭회로를 사용하였다. 설계된 회로는 0.65㎛ 2-poly, 2-metal CMOS 공정을 사용하여 IC로 제작되었다. 칩 면적은 0.9㎜×0.4㎜이다. 측정 결과 설계된 트랜스폰더 IC는 인식거리 내에서 약 20∼25%의 일정한 감폭율을 보이며, 125㎑의 RF에 대해 3.9kbps의 데이터 전송속도를 보인다. 트랜스폰더 칩의 전력소모는 읽기 모드시 약 100㎼이다. 인식거리는 약 7㎝이다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.119-124
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• 2008

Transimpedance amplifier(TIA) is the most significant element to determine the performance of the optical receiver, and thus the TIA must satisfy tile design requirements of high gain and wide bandwidth. In f)is paper, we propose a novel single chip optical receiver that exploits an analog adaptive equalizer and a limiting amplifier to enhance the gain and bandwidth performance, respectively. The proposed optical receiver is designed by using a $0.13{\mu}m$ CMOS process and its post-layout simulations show $120dB{\Omgea}$ transimpedance gain and 5.88GHz bandwidth. The chip core occupies the area of $0.088mm^2$, due to utilizing the negative impedance converter circuit rather than using on-chip passive inductors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.632-638
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• 2011

This paper presents on-chip Design-for-Testability (DFT) circuit for radio frequency System-on-Chip (SoC) applications. The proposed circuit measures functional specifications of RF integrated circuits such as input impedance, gain, noise figure, input voltage standing wave ratio (VSWRin) and output signal-to-noise ratio (SNRout) without any expensive external equipment. The RF DFT scheme is based on developed theoretical expressions that produce the actual RF device specifications by output DC voltages from the DFT chip. The proposed DFT showed deviation of less than 2% as compared to expensive external equipment measurement. It is expected that this circuit can save marginally failing chips in the production testing as well as in the RF system; hence, saving tremendous amount of revenue for unnecessary device replacements.