• 전자공학회논문지 IE
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• v.47 no.2
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• pp.13-20
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• 2010

This paper describes a current mode PWM DC-DC converter IC for battery charger and supply power converter for portable electronic devices. The maximum supply voltage of IC is 40[V] and 2.8[V]~330[V] DC input power is converted to higher or programmed DC voltage according to external resistor ratio or wire winding ratio of transformer. The maximum supply output current is 3[A] over and voltage error of output node is within 3[%]. The whole circuit needed current mode PWM DC-DC converter circuit is designed. The package dimensions and number of external parts are minimized in order to get a smaller hardware size. The power consumption is smaller then 1[mW] at stand by period with supply voltage of 3.6[V] and maximum energy conversion efficiency is about 86[%]. This device has been designed in a 0.6[um] double poly, double metal 40[V] CMOS process and whole chip size is 2100*2000 [um2].

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.174-174
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• 2009

현재 전자부품용으로 사용되는 유리프리트의 경우 PbO계를 주로 사용하고 있다. 최근 환경규제에 따른 PbO 사용이 제한됨에 따라 이를 대체할 Pb-free 유리 조성에 대한 연구가 활발히 진행 중이다. Pb-free계로서는 $Bi_2O_3$계, $B_2O_3$계가 주로 연구되고 있으나 소성 온도가 $500^{\circ}C$이상으로 높고 또한 $Bi_2O_3$ 계는 중금속이기 때문에 문제가 있다. 본 연구에서는 $400^{\circ}C$ 미만 소성이 가능한 SnO-$P_2O_5$계를 기본 조성계로 선택하고 열적, 전기적, 화학적 특성을 개선하기 위해 $R_2O_3$(R=Al, B), RO(R=Mg, Zn, Ca, Ba) 를 첨가하였다. 개선된 조성으로 샘플을 만들고 이를 대상으로 실제 전자부품 생산 공정에 적용 실험을 진행 하였다. 실험에 사용된 전자 부품은 소형 칩 베리스터로 생산 공정에서 코팅용 유리프리트와 파우더를 절연체로서 전면에 코팅하게 된다. 유리프리트를 코팅함으로서 누설 전류를 차단하고 생산 공정시 베리스터 내부를 보호하게 된다. 실험에 사용된 샘플의 열적 특성은 TMA로, 전기적 절연 특성은 고 절연저항 측정기로 측정하였고 내 산성과 내 알칼리성도 측정하였다. 샘플을 이용하여 완성된 칩 베리스터의 성능은 고온, 내습 신뢰성 TEST(고온:$150^{\circ}C$ 12HR, 내습:$85^{\circ}C$-85%12HR)로 실험하여 합부판정 (Leakage current <10uA)을 내려 완성품과 불량품을 가려내었다.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.18 no.4
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• pp.160-164
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• 2008

Insulating and conducting 12CaO ${\cdot}7Al_2O_3$ (Cl2A7)-doped indium tin oxide (ITO) (ITO:Cl2A7 insulator and electride) thin films were deposited on glass substrates by an RF magnetron co-sputtering method with increasing number of insulating and conducting Cl2A7 target chips. The structural, electrical and optical properties of these films were investigated. The carrier concentration decreased and resistivity increased in the films with increasing number of Cl2A7 target chips. The optical transmittance of all of the thin films was above 80 % in the visible wavelength range. The structural property and surface roughness of the films were examined and the decrease of crystallinity and surface roughness was strongly dependent on the change of grain size.

• Journal of Satellite, Information and Communications
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• v.10 no.4
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• pp.6-11
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• 2015

The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different GPNS(Gate to Primary $N^+$ Diffusion Space) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device with FPW(Full P-Well) structure and non-CPS(Counter Pocket Source) implant shows typical SCR-like characteristics with low on-resistance(Ron), low snapback holding voltage(Vh) and low thermal breakdown voltage(Vtb), which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW(Partial P-Well) structure and optimal CPS implant demonstrate the improved ESD protection performance as a function of GPNS variation. GPNS was a important parameter, which is satisfied design window of ESD protection device.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.3
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• pp.283-289
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• 2018

A PLL with an unipolar charge pump and a loop filter consisting of sample-hold capacitor and Fvco-sampled feedforward loop filter. The proposed PLL not only reduces the chip area by replacing the resistance to a switch and a small capacitor but also reduces the variation of ${\Delta}VLPF$ and ${\Delta}{\Delta}VLPF$ to 1/6 and 1/5 respectively. The variation of ${\Delta}VLPF$ is related to the phase noise of VCO output and that of ${\Delta}{\Delta}VLPF$ is proportional to reference spurs. It has been simulated and verified with a 1.8V $0.18{\mu}m$ CMOS process and shown a good phase noise characteristics. We plan to fabricate chip based on the simulations and check performance.

• 전자공학회논문지 IE
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• v.46 no.1
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• pp.16-22
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• 2009

Integrated circuit of a pulse-type neuron for Hodgkin-Huxley model is implemented in a $0.5{\mu}m$ 1 poly 2 metal CMOS technology. Proposed pulse-type neuron model consist of input stage with summing function and pulse generating block which make neuron pulse above threshold value. Pulse generating circuit consist of several transistors, capacitors and negative resistor with a charge supply function. SPICE simulation results show that neuron pulse is generated above threshold current of 70 nA. Measurements of the fabricated pulse type neuron chip in condition of 5 V power supply are shown and compared with the simulated results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.11 s.102
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• pp.1114-1122
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• 2005

In this paper, the study of a design, fabrication and measurement of the receiver MMIC LNA, mixer for S-band application is described. The LNA is designed by 2-stage common source. The mixer is composed of active LO and RF balun to integrate on a chip and applied a newly proposed bias circuit to compensate the process variations of active devices. The LNA has 15.51 dB-gain and 1.02dB-Noise Figure at 2.1 GHz. The conversion gain of the mixer is -12 dB, IIP3 is approximately 4.25 dBm and port-to-port isolation is over 25 dB. The newly proposed bias circuit is composed of a few FETs and resistors, and can compensate the variation of the threshold voltage by the process variations, temperature changes and etc. The designed chip size is $1.2[mm]\times1.4[mm]$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.91-97
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• 2013

In this paper, a current steering 10-bit CMOS D/A converter to drive a NTSC/PAL analog TV is proposed. The proposed D/A converter has a 50MS/s operating speed with a 6+4 segmented type. Further, in order to minimize the device mismatch, a self-calibration bias technique with a fully integrated termination resistance is discussed. The chip has been fabricated with a 3.3V 0.11um 1-poly 6-metal CMOS technology. The effective chip area is $0.35mm^2$ and power consumption is about 88mW. The experimental result of SFDR is 63.1dB, when the input frequency is 1MHz at the 50MHz of sampling frequency.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.2
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• pp.146-153
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• 2008

Integrated humidity sensor system with two stages operational amplifier has been designed and fabricated by $0.8{\mu}m$ analog mixed CMOS technology. The system (28 pin and $2mm{\times}4mm$) consisted of Wheatstone-bridge type humidity sensor, resistive type humidity sensor, temperature sensors and operational amplifier for signal amplification and process in one chip. The poly-nitride etch stop process has been tried to form the sensing area as well as trench in a standard CMOS process. This modified technique did not affect the CMOS devices in their essential characteristics and gave an allowance to fabricate the system on same chip by standard process. The operational amplifier showed the stable operation so that unity gain bandwidth was more than 5.46 MHz and slew rate was more than 10 V/uS, respectively. The drain current of n-channel humidity sensitive field effect transistor (HUSFET) increased from 0.54 mA to 0.68 mA as the relative humidity increased from 10 to 70 %RH.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.2
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• pp.333-338
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• 2008

In this paper, a new NMOS current-mirror type bridge rectifier for driving RFID chips, whose minimum input voltage required to obtain the effective DC output voltage is low enough and whose power dissipation can be reduced than that of conventional one, is proposed. The designed rectifier is able to supply high enough and well-rectified DC voltages to drive RFID transponder chips for the frequency range of 13.56 MHz HF(for ISO 18000-3), 915 MHz UHF(fur ISO 18000-6), and 2.45 GHz microwave(for ISO 18000-4). Output characteristics of the proposed rectifier are analyzed with the high frequency equivalent circuit. And the circuitry method for effective reducing of the gate leakage current due to the increasing of operating frequency is also proposed theoretically. Using this method, the power consumption of $100\;{\mu}W$ and the DC output voltage of 2.13V for 3V peak-to-peak input voltage and $45\;K{\Omega}$ load resistance are obtained. Compared to conventional one, the proposed rectifier operates in more stable and shows superior characteristics in UHF and microwave frequencies.