• Korean Journal of Materials Research
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• v.9 no.3
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• pp.288-294
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• 1999

In the flip chip interconnection using solder bump, the Under Bump Metallurgy (UBM) is required to perform multiple functions in its conversion of an aluminum bond pad to a solderable surface. In this study, various UBM systems such as $Al 1\mu\textrm{m} / Ti 0.2\mu\textrm{m} / Cu 5\mu\textrm{m}, Al 1\mu\textrm{m} / Ti 0.2\mu\textrm{m} / Cu 1\mu\textrm{m}, al 1\mu\textrm{m}/Ni 0.2\mu\textrm{m} / Cu 1\mu\textrm{m} and Al 1\mu\textrm{m}/Pd 0.2\mu\textrm{m} / Cu 1\mu\textrm{m}$ for flip chip interconnection using the low melting point eutectic 63Sn-37Pb solder were investigated and compared to their metallurgical properties. $100\mu\textrm{m}$ size bumps were prepared for using an electroplating process. The effects of the number of reflows and aging time on the growth of intermetallic compounds(IMC) were investigated. $Cu_6Sn_5$ and $Cu_3Sn$ IMC were abserved after aging treatment in the UBM system with thick coper $(Al 1\mu\textrm{m}/Ti 0.2\mu\textrm{m}/Cu 5\mu\textrm{m})$. However only the $Cu_6Sn_5$ was detected in the UBM system with $1\mu\textrm{m}$ thick copper even after 2 reflow and 7 day aging at $150^{\circ}C$. Complete Cu consumption by Cu-Sn IMC growth gives rise to a direct contact between solder inner layer such as Ti, Ni and Pd, and hence to possibly cause reactions between two of them. In this study, however, only for the Pd case, IMC of PdSn. was observed by Cu consumption. UBM interfacial reactions with s이der affected the adhesion strength ot s이der balls after s이der reflow and annealing treatment.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.49-56
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• 2012

Recently, by the trends of electronic package to be smaller, thinner and more integrative, fine bump is required. but It can result in the electrical short by reduced cross-section of UBM and diameter of bump. Especially, the formation of IMCs and KV can have a significant affects about electrical and mechanical properties. In this paper, we analyzed the thermal deformation of flip-chip bump by using FEM. Through Thermal Cycling Test (TCT) of flip-chip package, We analyzed the properties of the thermal deformation. and We confirmed that the thermal deformation of the bump can have a significant impact on the driving system. So we selected IMCs thickness and bump diameter as variable which is expected to have implications for characteristics of thermal deformation. and we performed analysis of temperature, thermal stress and thermal deformation. Then we investigated the cause of the IMC's effects.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.2
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• pp.154-160
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• 2009

This paper describes a wide bandwidth RFID tag antenna design for protection of connection part between chip and antenna. A proposed tag antenna size, a resonant frequency and bandwidth are $53{\times}10{\times}1\;mm$, 900 MHz and 800 MHz($500{\sim}1,300\;MHz$) at -10 dB below, respectively. The dielectric materials with different relative permittivity such as polyethylene, glass and silicon were applied for protection of connection part between the proposed antenna and chip on the way of whole and partial housing. The measured return loss and radiation pattern agreed well with the calculation results. The read range of the proposed tag antenna without any housing and of tag antenna with housing covered over all by silicon with 3 mm thickness were observed about 5 m and 4 m, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.6
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• pp.595-601
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• 2013

This paper presents an optimized design of a millimeter-wave on-chip dipole antenna using CMOS process. The serious flaw of the antenna using CMOS process is low radiation efficiency because of high permittivity and conductivity. To overcome the weakness, we need to widen radiation area in air and optimize distance between an antenna and a reflector. The radiation efficiency and bandwidth of the designed antenna are respectively 16.5 % and 22.3 % at 80 GHz. Systematic methods are attempt to analyze an effect on the antenna radiation efficiency. To widen radiation area in air, substrate cut angle and distance between the antenna and chip edge are adjusted. In addition, to optimize distance between an antenna and reflector, substrate thickness and distance between the antenna and a circuit ground plane are adjusted.

• Journal of Sensor Science and Technology
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• v.7 no.4
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• pp.279-284
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• 1998

A surface plasmon resonance (SPR) sensor system for the determination of sucrose concentration was constructed with a gold thin film sensing chip. The properties of gold thin film are critical factors in exciting surface plasmon resonance phenomena. Therefore in the present paper, the fabrication conditions of gold thin film were investigated to optimize the SPR phenomena. The optimum thickness was obtained as $545{\AA}$ with $43.75^{\circ}$ resonance angle and good surface roughness limitation. about $3{\AA}$. The linear resonance angle shifts and rapid response were observed from the sucrose concentrations ranged from 0 to 40wt%.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.07a
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• pp.157-160
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• 2001

APF optical link용 receiver를 하나의 바이폴라 칩으로 실현하기 위하여 수신파장 영역에서 고속.고감도 특성을 갖는 바이폴라 집적용 Si photodiode를 에피 두게 6$\mu\textrm{m}$(epi06)와 12$\mu\textrm{m}$(epi12)로 제작하고 이의 전기.광학적 특성을 조사하였다. 제작된 소자의 전기.광학적 특성을 -5 V의 동작전압에서 측정한 결과, 6 $\mu\textrm{m}$ 에피두께의 경우 접합커패시턴스와 암전류가 각각 4.8 pF와 2.6 pA로 나타났으며, 광신호 전류와 감도특성은 670 nm의 중심파장을 갖는 3.15 ㎼의 입사광 전력 아래에서 각각 0.568 $\mu\textrm{A}$와 0.18 A/W로 나타났다. 에피층의 두께가 12 $\mu\textrm{m}$의 경우 접합커패시턴스와 암전류는 각각 9.8 pF와 171.3 pA로 나타났으며, 광신호 전류와 감도특성은 3.679$\mu\textrm{A}$와 1.17 A/W로 나타났다. 제작된 두 소자는 적색 파장(λ$_{p}$=670nm)부근에서 최대 spectral response(λ$_{p}$=600nm at epi06, λ$_{p}$=700nm at epi12)를 보이고 있다.이고 있다.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.3
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• pp.31-36
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• 2002

The 2nd level solder joint reliability of 153 FC-BGA for high-speed SRAM (Static Random Access Memory) with the large chip on laminate substrate comparing to PBGA(Plastic Ball Grid Array) was studied in this paper. This work has been done to understand an influence as the mounting with single side or double sides, structure of package, properties of underfill, properties and thickness of substrate and size of solder ball on the thermal cycling test. It was confirmed that thickness of BT(bismaleimide tiazine) substrate increased from 0.95 mm to 1.20 mm and solder joint fatigue life improved about 30% in the underfill with the low young's modulus. And resistance against the solder ball crack became twice with an increase of the solder ball size from 0.76 mm to 0.89 mm in solder joints.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.7
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• pp.5021-5028
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• 2015

Previous studies have considered the permeability and construction method of paving materials, thus focusing on more practical issues rather than basic research of their properties. The present study investigated the possibility of using an elastic paving material having lesser thickness in the resurfacing of existing concrete or asphalt paved areas while satisfying the necessary conditions of resilience and water permeability. An alternative to complete reconstruction would reduce the amount of resource wastage and environmental pollution, as well as the cost of projects. This study investigated five variants of thickness (10, 13, 15, 20, 25mm) and three mixing ratios of binder to rubber chips (20, 22.5, 25%) to ascertain the ideal basic properties of each. The obtained test data revealed that a minimum thickness(10~25mm) of the elastic paving materials can be determined from a qualitative point of view, and alternatives should be provided to improve the durability of the paving material on account of the temperature sensitivity.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.2
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• pp.49-53
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• 2018

Recently, technologies for integrating various devices such as a flexible device, a transparent device, and a MEMS device have been developed. The key processes of heterogeneous device manufacturing technology are chip or wafer-level bonding process, substrate grinding process, and thin substrate handling process. In this study, the effect of Si substrate grinding process on the electrical properties of tin oxide thin films applied as transparent thin film transistor or flexible electrode material was investigated. As the Si substrate thickness became thinner, the Si d-spacing decreased and strains occurred in the Si lattice. Also, as the Si substrate thickness became thinner, the electric conductivity of tin oxide thin film decreased due to the lower carrier concentration. In the case of the thinner tin oxide thin film, the electrical conductivity was lower than that of the thicker tin oxide thin film and did not change much by the thickness of Si substrate.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.67-74
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• 2018

Thermoelectric thin film devices of the in-plane configuration consisting of 8 pairs of n-type $Bi_2Te_3$ and p-type $Sb_2Te_3$ legs were processed on Si submounts by electrodeposition. The thermoelectric generation characteristics of the thin film devices were investigated with respect to the apparent temperature difference ${\Delta}T$ caused by LED lighting as well as the change of the leg thickness. When ${\Delta}T$ was 7.4 K, the open circuit voltages of 6.1 mV, 7.4 mV, and 11.8 mV and the maximum output powers of 6.6 nW, 12.8 nW, and 41.9 nW were measured for the devices with the thermoelectric legs of which thickness were $2.5{\mu}m$, $5{\mu}m$, and $10{\mu}m$, respectively.