• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.91-92
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• 2007

이 논문에서는 다양한 채널길이에 따른 n-채널 다결정 실리콘 TFT의 특징을 보고한다. Excimer laser annealing (ELA)를 이용한 다결정 실리콘은 디스플레이의 재료로써 줄은 특성을 갖는다. 유리기판 위에 buffered oxide 층을 올리고 ELA 처리를 하여 다결정 실리콘을 제작 하였다. 그 위에 $SiO_2$, $SiN_x$를 증착시켜 n-채널 다결정 실리콘 TFT를 만들었다. 다양한 채널의 길이에 따른 n-채널 TFT의 문턱전압 ($V_{TH}$), ON/OFF 전류비($I_{ON}/I_{OFF}$), 포화 전륙(IDSAT)를 조사하였다. 그 결과 채널의 길이가 짧은 소자에서 더 줄은 TFT의 특징이 나타난다.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1281_1282
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• 2009

ICP-CVD를 이용하여 inverted staggered 구조를 갖는 미세결정 실리콘 (Nanocrystalline Silicon, nc-Si) 박막 트랜지스터(Thin Film Transistor, TFT)를 제작하였다. 또한, 소자의 특성과 전기적 안정성을 평가하였다. 실험 결과는 짧은 채널 길이를 갖는 nc-Si TFT가 긴 채널 길이의 소자보다 같은 드레인 전압 바이어스 하에서 덜 열화 됨을 알 수 있었다. 이는 드레인 전압 바이어스 하에서의 낮은 채널 캐리어 농도는 적은 defect state를 만들기 때문으로 짧은 채널 길이의 TFT가 긴 채널 길이의 TFT보다 $V_{TH}$ 열화가 적었다. 이러한 결과는 짧은 채널 길이의 nc-Si TFT가 디스플레이 분야에 있어 다양하게 응용될 것으로 기대된다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.222-225
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• 2000

In this paper, a synchronous CDMA system accepted for the cdma2000 standard is simulated to propose optimized reverse link power ratio and channel estimation lengths. Differently from IS-95, the pilot channel is used in the proposed system to estimate fading channel, so optimized estimation lengths are needed. Therefore, in this paper we analyze optimized estimation lengths which is needed to decide the power ratio of pilot channel and fundamental channel. From fixed estimation lengths, we calculate FER with various power ratio values.

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.971-973
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• 1999

채널길이에 따른 n-채널과 p-채널 poly-Si TFT's를 제작하고 그 전기적 특성을 분석하였다. n-채널과 p-채널소자는 공통적으로 기생바이폴라트 랜지스터현상(parasitic bipolar transistor action)에 의한 kink 효과, 전하공유(charge sharing)에 의한 문턱전압의 감소, 소오스와 드레인 근처의 결함에 의한 RSCE(reverse short channel effect) 효과, 수직전계에 의한 이동도의 감소, 그리고 avalanche 증식에 의한 S-swing의 감소가 나타났다. n-채널은 p-채널 보다 더 큰 kink, 이동도, S-swing의 변화가 나타났으며, 높은 드레인 전압에서의 문턱전압의 이동은 avalanche 증식(multiplication)에 의한 것이 더 우세한 것으로 나타났다. 누설전류의 경우, 채널 길이가 짧아짐에 따라 n-채널은 큰 증가를 나타냈으나 p-채널의 경우는 변화가 나타나지 않았다.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.118-125
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• 1999

A capacitance method to extract the metallurgical channel length of LDD MOSFET's, which is defined by the length between the metallurgical junction of substrate and source/drain under the gate, is presented. The gate capacitances of the finger type and plate type LDD MOSFET gate test patterns with same total gate area are measured. The gate bias of each pattern is changed, and the capacitances are measured with source, drain, and substrate bias grounded. The differences between two test pattern's capacitance data are plotted. The metallurgical channel length is extracted from the peak data at a maximum point using a simple formula. The numerical simulation using two-dimensional device simulator is performed to verify the proposed method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.6
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• pp.1399-1404
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• 2015

This paper analyzed the phenomenon of drain induced barrier lowering(DIBL) for the ratio of channel length vs. thickness of asymmetric double gate(DG) MOSFET. DIBL, the important secondary effect, is occurred for short channel MOSFET in which drain voltage influences on potential barrier height of source, and significantly affects on transistor characteristics such as threshold voltage movement. The series potential distribution is derived from Poisson's equation to analyze DIBL, and threshold voltage is defined by top gate voltage of asymmetric DGMOSFET in case the off current is 10^-7 A/m. Since asymmetric DGMOSFET has the advantage that channel length and channel thickness can significantly minimize, and short channel effects reduce, DIBL is investigated for the ratio of channel length vs. thickness in this study. As a results, DIBL is greatly influenced by the ratio of channel length vs. thickness. We also know DIBL is greatly changed for bottom gate voltage, top/bottom gate oxide thickness and channel doping concentration.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.401-406
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• 2015

The change of subthreshold swing for channel length of asymmetric double gate(DG) MOSFET has been analyzed. The subthreshold swing is the important factor to determine digital chracteristics of transistor and is degraded with reduction of channel. The subthreshold swing for channel length of the DGMOSFET developed to solve this problem is investigated for channel thickness, oxide thickness, top and bottom gate voltage and doping concentration. Especially the subthreshold swing for asymmetric DGMOSFET to be able to be fabricated with different top and bottom gate structure is investigated in detail for bottom gate voltage and bottom oxide thickness. To obtain the analytical subthreshold swing, the analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. As a result, subthreshold swing is sensitively changed according to top and bottom gate voltage, channel doping concentration and channel dimension.

• Proceeding of EDISON Challenge
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• 2015.03a
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• pp.347-349
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• 2015

본 연구에서는 MOSFET 제작방법중 하나인 이온주입법에서 다양한 변수로 작용하는 도핑농도, 에너지주입, 바탕농도의 역할에 대해서 알아보고 채널길이가 감소함에 따른 단채널효과를 억제할 수 있는 최적점에 대하여 분석하였으며 Ion Implant 이차원 시뮬레이션값과 비교하였다. 결과적으로 농도와 에너지주입 그리고 채널길이에 따른 MOSFET의 최적화된 모델을 분석하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.8
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• pp.9-16
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• 2000

MOS transistors are fabricated and evaluated for RF IC applications such as mobile communication systems using 0.35m CMOS process. Characteristics of MOSFETs are analyzed at various channel length, width and bias conditions. From the analysis, cut-off frequency ($f_T$) is independent on channel width but maximum oscillation frequency ($f_{max}$) tends to derease as the channel width increases. As channel length increases, $f_T$ and fmax decrease. $f_T$ is 22GHz and fmax is 28GHz at its maximum value. High frequency noise performance is improved with larger channel width and smaller channel length at same bias conditions. NFmin at 2GHz is 0.45dB as a minimum value. From the evaluation, MOSFETs designed using 0.35m CMOS process demonstrated a full potential for the commercial RF ICs for mobile communication systems near 2GHz. And optimization methods of the CMOS transistors for RF applications are presented in this paper.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.480-484
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• 2000

The channel length influence of n-channel Si-based FETs is investigated by computer simulation. Using a two-dimensional hydrodynamic model, devices having various gate length are examined. We have observed the characteristics of LDD model of MOSFET by investigating of their current, voltage, electric field and impact ionization. These devices are scaled using various factors. We have analyzed I-V characteristics and the effect of impact ionization according to channel length.