• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.17 no.8
• /
• pp.867-880
• /
• 1992

In this paper, a circuit design techniques for Improving the voltage gain of the GaAs MESFET single amplifier is presented. Also, various types of existing current mirror and proposed current mirror of new configuration are compared. To obtain the high differential mode gain and low common mode gain, bootstrap gain enhancement technique Is used and common mode feedback Is employed In the design of differential amplifier. The simulation results show that designed differential amplifier has differential gain of 57.66dB, unity gain frequency of 23.25GHz. Also, differential amplifier using common mode feedback with alternative negative current mirror has CMRR of 83.S8dB, stew rate of 3500 V /\ulcorners.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.23 no.6
• /
• pp.726-732
• /
• 2019

In this study, we proposed an asymmetric differential inductor to improve the linearity of differential power amplifiers. Considering the phase error between differential signals of the differential amplifier, the location of the center tap of the differential inductor was modified to minimize the error. As a result, the center tap was positioned asymmetrically inside the differential inductor. With the asymmetric differential inductor, the AM-to-AM and AM-to-PM distortions of the amplifier were suppressed. To confirm the feasibility of the inductor, we designed a 2.4 GHz differential CMOS PA for IEEE 802.11n WLAN applications with a 64-quadrature amplitude modulation (QAM), 9.6 dB peak-to-average power ratio (PAPR), and a bandwidth of 20 MHz. The designed power amplifier was fabricated using the 180-nm RF CMOS process. The measured maximum linear output power was 17 dBm, whereas EVM was 5%.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.33 no.2
• /
• pp.113-118
• /
• 2005

This paper shows a satellite battery cell voltage monitor system to make differential voltage measurements when one or both measurement points are beyond voltage range allowed by a conventional differential amplifier. This system is particularly useful for monitoring the individual cell voltage of series-connected cells that constitute a rechargeable satellite battery in which some cell voltages must be measured in the presence of high common mode voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.9 no.5
• /
• pp.660-667
• /
• 1998

In this paper, we used differential amplifiers to reduce crosstalk in a wireless in-house optical interconnection in which two channel beams are overlapped. Experimental results show that environmental optical noise is also reduced using the same principle. This method is realized very easily with differential amplifiers without any optical filters or electrical filters. It is very useful in short distance optical interconnections.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.6 s.360
• /
• pp.89-93
• /
• 2007

This paper presents the design and the implementation of input/output (I/O) interface circuits for 2.5 Gbps operation in a 3.3V 0.35um CMOS technology. Due to the differential transmission technique and low voltage swing, LVDS(low-voltage differential signaling) has been widely used for high speed transmission with low power consumption. This interface circuit is fully compatible with the LVDS standard. The LVDS proposed in this paper utilizes a telescopic amplifier. This circuit is operated up to 2.3 Gbps. The circuit has a power consumption of 25. 5mW. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.19 no.1
• /
• pp.14-19
• /
• 1982

A differential amplifier has been designed and fabricated using aluminum-gate PMOS technology, Only enhaneement-mode MOSFET's are used in the circuit and the dimensions of transistors have been determined using simulation program MSINC. The fabricated integrated circuit with +15V and -l5V power supplies shows an open-loop DC voltage gain of 42 dB, a common mode rejection ratio (CMRR) of 50 dB, and a Power consumption of 20mW.

• Journal of Korea Society of Industrial Information Systems
• /
• v.21 no.1
• /
• pp.61-70
• /
• 2016

This paper describes a new PMU(parametric measurement unit) design technique for automatic test equipment(ATE). Only one DDA(differential difference amplifier) is used to force the test signals to DUT(device under test), while conventional design uses two or more amplifiers to force test signals. Since the proposed technique does not need extra amplifiers in feedback path, the proposed PMU inherently guarantees stable operation. Moreover, to measure the response signals from DUT, proposed technique also adopted only one DDA amplifier as an IA(instrument amplifier), while conventional IA uses 3 amplifiers and several resistors. The DDA adopted two rail-to-rail differential input stages to handle full-range differential signals. Gain enhancement technique is used in folded-cascode type DDA to get open loop gain of 100 dB. Proposed PMU design enables accurate and stable operation with smaller hardware and lower power consumption. This PMU is implemented with 0.18 um CMOS process and supply voltage is 1.8 V. Input ranges for each force mode are 0.25~1.55 V at voltage force and 0.9~0.935 V at current force mode.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.28 no.5
• /
• pp.366-372
• /
• 2017

In this paper, the analysis of baluns that are inevitably required to design a differential low noise amplifier, The balun converts a single signal input from the antenna into a differential signal, which serves as an input to the differential amplifier. In addition, it protects the circuit from ESD(Electrostatic Discharge) coming through the antenna and helps with input matching. However, in the case of a passive balun used in general, since the AC signal is transmitted through electromagnetic coupling formed between two metal lines, it not only has loss without gain but also has the greatest influence on the total noise figure of the receiving end. Therefore, the design of a balun in a low-noise amplifier is very important, and it is important to design a balun in consideration of line width, line spacing, winding, radius, and layout symmetry that are necessary. In this paper, the factors to be considered for improving the quality factor of balun are summarized, and the tendency of variation of resistance, inductance, and capacitance of the balun according to design element change is analyzed. Based on the analysis results, it is proved that the design of input balun allows the design of low noise, high gain differential amplifier with gain of 24 dB and noise figure of 2.51 dB.

• Journal of Korea Society of Industrial Information Systems
• /
• v.19 no.3
• /
• pp.1-7
• /
• 2014

This paper describes the implementation of high speed comparator for the ATE (automatic test equipment) system. The comparator block is composed of continuous comparator, differential difference amplifier(DDA) and output stage. For the wide input dynamic range of 0V to 5V, and for the high speed operation (1~800MHz), high speed rail-to-rail amplifier is used in the first stage. And hysteresis circuits, pre-amp and latch are followed for high speed operation. To measure the difference of output signals between the two devices under test (DUTs), a DDA is applied because it can detect the differences of both common signals and differential signals. This comparator chip was implemented with $0.18{\mu}m$ BCDMOS process and can compare the signal difference of 5mV up to the frequency range of 800 MHz. The chip area of the comparator is $620{\mu}m{\times}830{\mu}m$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.8 s.338
• /
• pp.53-60
• /
• 2005

Recently, sub-micron CMOS technologies have taken the place of III-V materials in a number of areas in integrated circuit designs, in particular even for the applications of gjgabit optical communication applications due to its low cost, high integration level, low power dissipation, and short turn-around time characteristics. In this paper, a four-channel transimpedance amplifier (TIA) array is realized in a standard 0.35mm CMOS technology Each channel includes an optical PIN photodiode and a TIA incorporating the fully differential regulated cascode (RGC) input configuration to achieve effectively enhanced transconductance(gm) and also exploiting the inductive peaking technique to extend the bandwidth. Post-layout simulations show that each TIA demonstrates the mid-band transimpedance gain of 59.3dBW, the -3dB bandwidth of 2.45GHz for 0.5pF photodiode capacitance, and the average noise current spectral density of 18.4pA/sqrt(Hz). The TIA array dissipates 92mw p in total from a single 3.3V supply The four-channel RGC TIA array is suitable for low-power, high-speed optical interconnect applications.