• Journal of KIISE:Software and Applications
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• v.32 no.4
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• pp.247-257
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• 2005

Generally, the network topology design problem is characterized as a kind of NP-hard combinatorial optimization problem, which is difficult to solve with the classical method because it has exponentially increasing complexity with the augmented network size. In this paper, we propose the efficient approach with two phase that is comprised of evolutionary computation approach based on Prufer number(PN), which can efficiently represent the spanning tree, and a heuristic method considering 2-connectivity, to solve the highly reliable network topology design problem minimizing the construction cost subject to network reliability: firstly, to find the spanning tree, genetic algorithm that is the most widely known type of evolutionary computation approach, is used; secondly, a heuristic method is employed, in order to search the optimal network topology based on the spanning tree obtained in the first Phase, considering 2-connectivity. Lastly, the performance of our approach is provided from the results of numerical examples.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.391-396
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• 2013

In this paper, for HEVC decoding, an SAO hardware design with less processing time and reduced area is proposed. The proposed SAO hardware architecture introduces the design processing $8{\times}8$ CU to reduce the hardware area and uses internal registers to support $64{\times}64$ CU processing. Instead of previous top-down block partitioning, it uses bottom-up block partitioning to minimize the amount of calculation and processing time. As a result of synthesizing the proposed architecture with TSMC $0.18{\mu}m$ library, the gate area is 30.7k and the maximum frequency is 250MHz. The proposed SAO hardware architecture can process the decode of a macroblock in 64 cycles.

• Journal of IKEEE
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• v.20 no.4
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• pp.398-411
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• 2016

SVM, a machine learning method, is widely used in image processing for it's excellent generalization performance. However, to add other data to the pre-trained data of the system, we need to train the entire system again. This procedure takes a lot of time, especially in embedded environment, and results in low performance of SVM. In this paper, we implemented an SVM trainer and classifier in an FPGA to solve this problem. We parlallelized the repeated operations inside SVM and modified the exponential operations of the kernel function to perform fixed point modelling. We implemented the proposed hardware on Xilinx ZC 706 evaluation board and used TSR algorithm to verify the FPGA result. It takes about 5 seconds for the proposed hardware to train 2,000 data samples and 16.54ms for classification for $1360{\times}800$ resolution in 100MHz frequency, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.4
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• pp.727-736
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• 2009

In this paper, the $arccos(cos^{-1})$ arithmetic unit for mobile graphics accelerator is designed. The mobile vector graphics applications need tight area, execution time, power dissipation, and accuracy constraints compared to desktop PC applications. The designed processor adopts 2nd-order polynomial approximation scheme based on IEEE floating point data format to satisfy speed and accuracy conditions and reduces area via hardware sharing structure. The arccosine processor consists of 15,280 gates and its estimated operating frequency is about 125Mhz at operating condition of $0.35{\mu}m$ CMOS technology. Because the processor can execute arccosine function within 7 clock cycles, it has about 17 MOPS(million arccos operations per second) execution rate and can be applicable to mobile OpenVG processor. And because of its flexible architecture, it can be applicable to the various transcendental functions such as exponential, trigonometric and logarithmic functions via replacement of ROM and minor hardware modification.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.20 no.5
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• pp.81-88
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• 2010

Sun et al. proposed a new design of wearable token system for security of mobile devices, such as a notebook and PDA. In this paper, we show that Sun et al.'s system is vulnerable to off-line password guessing attack and man in the middle attack based on known plain-text attack. We propose an improved scheme which overcomes the weaknesses of Sun et al.'s system. The proposed protocol requires to perform one modular multiplication in the wearable token, which has low computation ability, and modular exponentiation in the mobile devices, which have sufficient computing resources. Our protocol has no security problem, which threatens Sun's system, and known vulnerabilities. That is, the proposed protocol overcomes the security problems of Sun's system with minimal overheads.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.4
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• pp.81-93
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• 2000

In a methodological approach to improve the processing performance of modulo exponentiation which is the primary arithmetic in RSA crypto algorithm, we present a new RSA hardware architecture based on high-radix modulo multiplication and CRT(Chinese Remainder Theorem). By implementing the modulo multiplier using radix-16 arithmetic, we reduced the number of PE(Processing Element)s by quarter comparing to the binary arithmetic scheme. This leads to having the number of clock cycles and the delay of pipelining flip-flops be reduced by quarter respectively. Because the receiver knows p and q, factors of N, it is possible to apply the CRT to the decryption process. To use CRT, we made two s/2-bit multipliers operating in parallel at decryption, which accomplished 4 times faster performance than when not using the CRT. In encryption phase, the two s/2-bit multipliers can be connected to make a s-bit linear multiplier for the s-bit arithmetic operation. We limited the encryption exponent size up to 17-bit to maintain high speed, We implemented a linear array modulo multiplier by projecting horizontally the DG of Montgomery algorithm. The H/W proposed here performs encryption with 15Mbps bit-rate and decryption with 1.22Mbps, when estimated with reference to Samsung 0.5um CMOS Standard Cell Library, which is the fastest among the publications at present.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.7
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• pp.413-423
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• 2014

With the increasing demands on high data rate, there has been growing interests in multi-input multi-output (MIMO) technology based on spatial multiplexing (SM) since it can transmit independent information in each spatial stream. Recent standards such as 3GPP LTE-advanced and IEEE 802.11ac support up to eight spatial streams, and massive MIMO and mm-wave systems that are expected to be included in beyond 4G systems are considering employment of tens to hundreds of antennas. Since the complexity of the optimum maximum likelihood based detection method increases exponentially with the number of antennas, low-complexity SM MIMO detection becomes more critical as the number of antenna increases. In this paper, we first review the results on the detection schemes for SM MIMO systems. In addition, massive MIMO reception schemes based on simple linear filtering which does not require exponential increment of complexity will be explained, followed by brief description on receiver design for future high dimensional SM MIMO systems.

• Journal of IKEEE
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• v.25 no.3
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• pp.479-484
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• 2021

This paper proposed and designed a structure to achieve high performance with a small number of cores in GPGPU with SIMT structure. GPGPU for application to mobile devices requires a structure to increase performance compared to power consumption. In order to reduce power consumption, the number of cores decreased, but to improve performance, the size of the warp scheduler for managing threads was set to 4, which was greatly reduced than 32 of general GPGPU. Reducing warp size can reduce the number of idle cycles in pipelines and efficiently apply memory latency to reduce miss penalty when accessing cache memory. The designed GPGPU measured computational performance using a test program that includes floating point operations and measured power consumption through a 28nm CMOS process to obtain 104.5GFlops/Watt as a performance per power. The results of this paper showed about four times better performance per power compared to Tegra K1 of Nvidia

• Journal of the Korean Association of Geographic Information Studies
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• v.23 no.2
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• pp.21-35
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• 2020

Vegetation information is a very important factor used in various fields such as urban planning, landscaping, water resources, and the environment. Vegetation varies according to canopy density or chlorophyll content, but vegetation vitality is not considered when classifying vegetation areas in previous studies. In this study, in order to satisfy various applied studies, a study was conducted to set a threshold value of vegetation index considering vegetation vitality. First, an eBee fixed-wing drone was equipped with a multi-spectral camera to construct optical and near-infrared orthomosaic images. Then, GIS calculation was performed for each orthomosaic image to calculate the NDVI, GNDVI, SAVI, and MSAVI vegetation index. In addition, the vegetation position of the target site was investigated through VRS survey, and the accuracy of each vegetation index was evaluated using vegetation vitality. As a result, the scenario in which the vegetation vitality point was selected as the vegetation area was higher in the classification accuracy of the vegetation index than the scenario in which the vegetation vitality point was slightly insufficient. In addition, the Kappa coefficient for each vegetation index calculated by overlapping with each site survey point was used to select the best threshold value of vegetation index for classifying vegetation by scenario. Therefore, the evaluation of vegetation index accuracy considering the vegetation vitality suggested in this study is expected to provide useful information for decision-making support in various business fields such as city planning in the future.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.