• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.8
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• pp.717-724
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• 2016

This paper presents design of a 40 GHz CMOS PLL frequency synthesizer for a 60 GHz sliding-IF RF transceiver. For stable locking over a wide bandwith for a injection-locked frequency divider, an inductive-peaking technique is employed so that it ensures the PLL can safely lock across the very wide tuning range of the VCO. Also, Injection-locked type LC-buffer with low-phase noise and low-power consumption is added in between the VCO and ILFD so that it can block any undesirable interaction and performance degradation between VCO and ILFD. The PLL is designed in 65 nm CMOS precess. It covers from 37.9 to 45.3 GHz of the output frequency. and its power consumption is 74 mA from 1.2 V power supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9B
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• pp.1683-1689
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• 1999

We have implemented Frequency bandwidth expander with frequency upconverting by VCO drift canceller and comb generator. Te output of the low frequency synthesizer which the output frequency is 220~280MHz(Resolution : 5MHz) is expanded to 1660~2140MHz by this system. The phase noise of this system only depends on the phase noise of comb generator and low frequency synthesizer. The phase noise of VCO don’t influence at the frequency expander because the drift of VCO cancel out. When we control the output of VCO, the output frequency of this system is varied by 60MHz x N as filter banker. The switching time and the spurious of the frequency expander is below 3usec, -55dBc respectively. This system easily expands bandwidth additively by expanding the output bandwidth of the VCO. We can apply the frequency expander to very wide band microwave synthesizer which has fast switching time.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.6
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• pp.959-968
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• 2000

In this paper, a low phase noise frequency synthesizer used to TX local oscillator in BWLL RF tranceiver is presented. The phase-locked stable 25GHz-band frequencies in BWLL TX LO are obtained by using 2 GHz baseband frequency synthesizer, sixth-harmonic frequency multiplier and frequency doubler at 12 GHz band frequency input. The 25 GHz band frequency synthesizer presented in this paper has 3-output frequencies at 24.92 GHz, 25.10 GHz, 25.26 GHz. At 24.92 GHz frequency the synthesizer has 0.44 dBm output power and shows -87.93 dBc/Hz(a 10 KHz), -109.54 dBc/Hz (a100 KHz) phase noise characteristics .

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.6
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• pp.546-551
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• 2002

In this paper, a triple controlled type DDFS-driven PLL frequency synthesizer with reduced complexity is used to show its applications for broadband wireless communication systems by frequency synthesis control. Since the proposed DDFS-driven PLL synthesizer is very simplified to use only phase accumulator in DDFS, it improves the switching speed and power consumption than the conventional DDFS-driven PLL frequency synthesizer. It is appropriate for applications with requirements of broadband, low-power consumption and high switching speed, since the proposed synthesizer can cover a wide range of frequency bands by the triple frequency control parameters. Method and results of frequency control parameters assignment are shown for the several frequency bands applications such as GSM, IMT-2000, Bluetooth and PCS system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.333-341
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• 2015

In this paper, a 0.5~4 GHz frequency synthesizer having good phase noise performance is proposed. Wideband output frequencies of the synthesizer were synthesized using DDS(Direct Digital Synthesizer) and analog direct frequency synthesis technology in order to obtain fast settling time. Also in order to get good phase noise performance, 2.4 GHz DDS clock was generated by VCO(Voltage Controlled Oscillator) which was locked by the 100 MHz reference oscillator using SPD(Sample Phase Detector). The phase noise performance of wideband frequency synthesizer was estimated and the results were compared with the measured ones. The measured phase noise of the frequency synthesizer was less then -121 dBc @ 100 kHz at 4 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.9
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• pp.903-911
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• 2014

This paper proposes a high speed frequency synthesizer with dual phase-locked loop(PLL) structure to improve phase noise level and shape in a wideband receiver. To reduce phase noise and fractional spur, a output frequency of $1^{st}$ PLL used as reference frequency of $2^{nd}$ PLL is changed. The frequency synthesizer has been designed with 1 Hz frequency resolution using digital NCO in 6.5~8.5 GHz wide spectrum. The measured results of the fabricated frequency synthesizer show that the output power is about -3 dBm, the maximum lock-in time and phase noise are within 60 us and -95 dBc/Hz at 10 kHz offset, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.61-67
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• 2009

This paper reports an Integer-N phase locked loop (PLL) frequency synthesizer which was implemented in a 250nm standard digital CMOS process for a UHF RFID wireless communication system. The main blocks of PLL have been designed including voltage controlled oscillator, phase frequency detector, and charge pump. The LC VCO has been used for a better noise property and low-power design. The source and drain juntions of PMOS transistors are used as the varactor diodes. The ADF4111 of Analog Device has been used for the external pre-scaler and N-divider to divide VCO frequency and a third order RC filter is designed for the loop filter. The measured results show that the RF output power is -13dBm with 50$\Omega$ load, the phase noise is -91.33dBc/Hz at 100KHz offset frequency, and the maximum lock-in time is less than 600us from 930MHz to 970MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.10B
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• pp.1464-1469
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• 2001

본 논문에서는 디지털 하이브리드 위상고정루프(Digital Hybrid Phase-Locked Loop, DHPLL) 주파수 합성기 구조에서 고 순도 스펙트럼과 초고속 스위칭 속도를 위한 설계기술을 제안한다. D/A 변환기 출력으로 전압제어발진기(Voltage Controlled Oscillator, VCO)를 구동하는 개 루프(open-loop) 구성 방식과 기존 위상고정루프(Phase Locked Loop, PLL)의 폐 루프(closed-loop) 구성 방식을 혼합한 하이브리드 구조의 주파수 합성기를 고려하여, 시스템 변수(개 루프 대역과 위상 여유)와 성능 파라미터(정착시간, 위상 잡음, 그리고 최대 오버슈트(Max. overshoot)의 관계를 연구하였다. 그리고 이 관계를 통해 스펙트럼 순도와 스위칭 속도를 향상시키기 위한 최적의 3가지 설계방안을 제시한다. 컴퓨터 시뮬레이션 결과, 주파수 스위칭 과정에서 발생하는 최대 오버슈트가 0.0991%이고 완전 정상상태 도달시간은 0.288msec이다. offset 주파수 10KHz에서 위상 잡음은 -128.15dBc이다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.4
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• pp.421-427
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• 2004

A low cost solution employing harmonic oscillation to the frequency synthesizer at 5.8 ㎓ is proposed. The proposed frequency synthesizer is composed of 2.9 ㎓ PLL chip, 2.9 ㎓ oscillator, and 5.8 ㎓ buffer amplifier The measured data shows a frequency Outing range of 290 ㎒, ranging from 5.65 to 5.94 ㎓ about 0.5 ㏈m of output power, and a phase noise of -107.67 ㏈c/㎐ at the 100 ㎑ offset frequency. All spurious signals including fundamental oscillation power(2.9 ㎓) are suppressed at least 15 ㏈c than the desired second harmonic signal.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.11
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• pp.1178-1185
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• 2009

In this paper, a wideband ultra-high speed & high purity discrete frequency synthesizer having minimum 2.5 MHz step size was proposed. To achieve fast and wideband operation, discrete frequencies were synthesized by mixing of 3 different pre-synthesized 16 frequencies made from fixed PLL and frequency dividers. Frequencies with discrete 2.5 MHz step were produced in 710~1,610 MHz. The measured hopping response time was 350 nsec average, output level was 21.5 dBm average with 2.65 dB flatness, spurious and harmonics level were suppressed below -60 dBc, and phase noise was -94 dBc/Hz@100 Hz. Also, a new measurement method for synthesizer response time was described.