• Journal of Advanced Navigation Technology
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• v.24 no.6
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• pp.557-565
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• 2020

In order for thermal degradationIn, excore nuclear flux monitoring system, as a monitoring and signal processing methodology of reactor power, monitors neutron pulses generated during nuclear fission as frequency status, and converts them into DC voltage, and then log values resultantly. The methods realy applied in the nuclear power plant are to construct combination of counters and flip-flops, or diodes and capacitors up to now. These methodes are reliable for relative high frequencies, while not credible for reasonable low frequencies or extreme low values. Therefore, we developed the circuit that converts frequencies into DC voltages, into and into log DC values in the wide range from low Hz to several hundred high kHz. We proved their validities through testing them using real data used in nuclear power plant and analyzed their results. And, these methods will be used to measure the neutron level of excore nuclear flux monitoring system in nuclear power plant.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.613-623
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• 2000

Digital TV tuner for 8-VSB modulation was developed with satisfying the requirements of ATSC. The double frequency conversion and the active tracking filter in the front-end were used to reduce interference of the adjacent channels and multi-channels, which suppress If beat and image band. However, it was impossible to get frequency mapping between tracking filter and first VCO(Voltage Controlled Oscillator) in the double conversion digital TV tuner differing from conventional NTSC tuner. This paper, therefore, suggests the available structure and a new method for automatic frequency selection by obtaining the mapping of frequency characteristic over tracking voltage and the combined hardware which compose of Micro-controller, EEPROM, D/A(Digital-to-Analog Converter), OP amp and switch driver to solve above problems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.12
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• pp.691-698
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• 2014

An L-band single side band(SSB) mixer with CMOS switches and a C-band quadrature voltage-controlled oscillator(QVCO) have been developed using the TowerJazz 0.18-um RFCMOS process. The SSB mixer exhibits a conversion gain of 6.6 ~ 7.5 dB with a 70-dBc image rejection ratio and 65-dBc port isolation. The oscillation frequency range of the QVCO is 6.2 ~ 6.7 GHz with an output power of 4~6 dBm. For measurement, 1.8 V supply voltage is used while drawing 36 mA for the mixer and 23 mA for the QVCO.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.717-718
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• 2013

The output frequency of VCO(Voltage-Controlled Oscillator) with input frequency is changed if CMOS channel length and width are changed. In this paper, the electrical characteristics of VCO circuit is used as a part of FLL circuit are simulated with CMOS channel width. And the method is introduced to improve the reliability characteristics of VCO with channel width variation.

• 전기의세계
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• v.25 no.4
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• pp.38-41
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• 1976

최근 전력용 반도체소자를 이용하여 전력의 변환과 제어를 하는 Power electronics가 많은 발전을 하고 있는데 이것을 가장 많이 이용하는 분야는 전동기의 가변속 구동이다. 이중에서 교류전동기의 구동을 위한 가변 주파수 제어장치의 구성을 보면 전압형 Inverter, 전류형 Inverter 및 Cycloconverter등에 의한 것으로 대별된다. 교류전동기의 가변주파수 제어는 농형유도전동기의 경우가 가장 많고 동기전동기는 약간 있는 정도이다. 여기서는 이러한 제어에 쓴이는 전압형 Inverter의 대표적인 회로와 최근에 개발된 펄스폭 제어 Inverter의 동작 원리 및 특징등에 대하여 소개하고저 한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2716-2724
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• 2012

In this paper, a Phase Difference-to-Voltage Converter (PDVC) has been introduced into a conventional fractional-N PLL to suppress fractional spurs. The PDVC controls charge pump current depending on the phase difference of two input signals to phase frequency detector. The charge pump current decreases as the phase difference of two input signals increase. It results in the reduction of fractional spurs in the proposed fractional-N PLL. The proposed fractional-N PLL with PDVC has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.5
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• pp.949-954
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• 2007

In this work, temperature stable frequency-to-voltage converter is proposed. In FVC circuit input frequency is converted into output voltage signal. A FLL is similar to PLL in the way that it generates an output signal which tracks an input reference signal. A PLL is built on a phase detector, a charge pump, and a low pass filter. However, FLL does not require the use of the phase detector, the charge pump and low pass filter. The FVC is designed by using $0.25{\mu}m$ CMOS process technology. From simulation results, the variation of output voltage is less than ${\pm}2%$ in the temperature range $0^{\circ}C\;to\;75^{\circ}C$ when the input frequency is from 70MHz to 140MHz.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.309-315
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• 1998

This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for Integrated Services Digital Network (ISDN) applications. The proposed ADC based on the improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADCs to increase throughput rate. Moreover, the ADC employs the interpolation technique in the back-end subranging ADCs far residue signal processing to minimize die area and power consumption. The fabricated and measured prototype ADC in a 0.8 um n-well double-poly double-metal CMOS process typically shows a 52 MHz sampling rate at a 5 V supply voltage with 230 mW, and a 40 MHz sampling rate at a 3 V power supply with 60 mW power consumption.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.331-334
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• 2004

본 논문에서는 클록의 duty ratio가 변하였을 때, 그 클록의 duty ratio를 $50\%$의 duty ratio로 만들어 주는 Pulse Width Control Loop Circuit을 설계하였다. 기존의 논문에서는 duty ratio를 변화시키기 위해 각 duty ratio 마다 알맞은 제어 전압을 공급해하는 문제점이 있었다. 본 논문은 제어 전압이 변하지 않고 일정한 전압으로도 duty ratio를 변화시킬 수 있게 하여, 제어 전압 변화에 대한 문제점을 해결하였다. 설계, 시뮬레이션 결과 기존의 논문보다 간단해진 회로 구성으로 더욱 높은 주파수에서 동작하였다. 그리고 settling 시간도 기존의 논문의 l00ns 이상에서 5ns로 줄어듦을 확인할 수 있었다. 본 논문은 3.3V의 공급 전압에서 $0.35{\mu}m$ CMOS공정을 이용하여 설계하였고 동작 주파수는 500MHz-2GHz였고, settling 시간은 10n이하였다.

• Proceedings of the KIPE Conference
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• 2012.11a
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• pp.149-150
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• 2012

본 논문에서는 배터리 팩을 구성하는 셀간의 전압편차를 이용한 이산 웨이블릿 변환(DWT;discrete wavelet transform) 기반 SOH(State-of-health) 예측방법을 소개한다. 충방전 전압은 DWT의 다해상도 분석(MRA;multi-resolution analysis)을 이용한 시간-주파수 분석을 통해 고주파 전압 성분(detail;$D_n$)과 저주파 전압 성분(approximation;$A_n$)으로 추가 분해되어 SOH 예측을 위한 추가정보를 제공한다. 각 성분의 통계처리(표준편차)를 통해 노화 이전과 이후의 성분값을 비교한다. 즉 프레시 배터리팩과 노화된 팩의 표준편차 기반 셀간 불균형을 서로 비교하여 SOH 예측이 가능하다.