• Journal of The Korean Association For Science Education
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• v.6 no.2
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• pp.53-62
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• 1986

본 연구의 목적은 한국 중 고등학교 학생들의 지적 발달의 특성을 조사 분석함으로써 교과서 및 교육과정의 개발에 필요한 기초자료를 얻으려는 것이다. 지역, 학년, 연령, 성 및 가정의 사회 경제적 지위에 따른 인지 발달 특성을 조사하였다. 연구의 대상은 전국을 대도시, 중 소도시, 농촌으로 유층화한 유층군집 표집방법에 의해 표집한 중학교 1학년부터 고등학교 2학년까지의 남 녀 학생이었다. 표집학생 수는 중학교가 18개교 54학급 3,164명이었고, 고등학교가 18개교 36학급 1,981명이었다. 가정의 사회 경제적 지위는 가정의 경제적 형편, 부의 직업, 부의 학력, 가정의 수입 정도를 고려하여 4계층으로 구분하였다. 사용된 도구는 지적 영역의 조사에 Piaget의 인지발달이론에 따른 논리발달 검사를 이용했다. 분석된 결과를 요약하면 다음과 같다. 첫째, 명제논리, 확률논리, 조합논리, 변인조작개념은 연령과 학년이 높아질수록, 대도시로 갈수록, 사회 경제적 지위가 높을수록 더욱 발달하는 경향이다. 둘째, 개념의 발달경향에 있어서 이원추리와 조합논리개념의 발달이 확률논리와 명제논리 개념의 발달보다 빠른 경향이다. 셋째, 한국의 중등학생 중에서 12세의 64.6%, 13세의 58.1%, 14세의 43.8%, 15세의 30.1%, 16세의 22.6%가 구체적 조작 후기에 도달해 있다. 넷째, 중등학생의 학년별 인지발달경향을 보면 중1의 69.8%, 중2의 51.1%, 중3의 47.4%, 고1의 21.6%, 고2의 21.7%가 구체적 후기의 발달수준이다.

• Corrugated packaging logistics
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• v.5 no.20
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• pp.131-144
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• 1997

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.41-45
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• 2017

This paper presents a method of constructing the efficiency multiple output switching function of the combinational logic systems. The proposed method reduce the optimized input variable pair and output variable pair after we obtained the final multiple output switching function which was time based multiplexing and obtained the common multiple end node extension logic decision diagram. Also the proposed method have an advantage of the cost, input-output node number, circuit simplification, increment of the arithmetic speed, and more regularity and extensibility compare with previous method.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.4
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• pp.7-13
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• 1978

This paper is concerned with the realization of sequential machines using shift-register modules as their memory elements. Other methods were to select shift-registers under the specific conditions and didn't consider the complexity of combinational circuits driving them. By using an integer valued function, all shift-registers with minimum length could be selected and an optimum assignment with lowest complexity could be obtained by comparing the number of input lines of combinational logic circuits driving them.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.4
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• pp.204-212
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• 2001

본 논문에서는 조합논리회로의 테스트 컴팩션을 위한 두 가지 효율적인 알고리즘을 제안한다. 제안된 알고리즘들은 각각 동적인 컴팩션 기법과 정적인 컴팩션 기법을 사용하고 있으며, 실험을 위해 기존의 ATPG시스템인 ATALANTA에 통합 구현하였다. ISCAS85와 ISCAS89(완전스캔 버전) 벤치마크 회로에 대한 실험에서 본 시스템은 기존에 발표된 다른 컴팩션 알고리즘에 비하여 보다 작은 테스트 집합을 보다 빠르게 생성하였으며, 실험 결과를 통하여 제안된 알고리즘들의 유효성을 입증할 수가 있었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1288-1293
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• 2005

This paper presents a design method for multiple-output combinational digital logic systems using time domain based on multiplexing(TDBM) and common multi-terminal extension decision diagrams(CMTEDD). The CMIEDDs represents extension valued multiple-output functions, while TDBM systems transmit several signals on a single lines. The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams(DDs), that is the common binary decision diagrams(CBDDs) and CMTEDDs. Also, we propose an algorithms to derive common multiple-terminal binary decision diagrams(CMTBDD) from CBDDs, and CMTEDDs from CMTBDDs. The CMTEDDs over CBDDs is more compactness in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes. In the logic design, each non-terminal nodes of an CBDDs and an CMTEDDs is realized by a multiplexer(MUX). In addition, we compare the proposed TDBM realization with the conventional one.

• Journal of The Korean Association of Information Education
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• v.14 no.4
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• pp.555-560
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• 2010

The purpose of this study is to investigate the effect of learning algorithm which uses real-life examples including the concept of algorithm on the logical thinking of elementary school students. For this purpose, the experiment was performed by pre-GALT test, a case selection of algorithm which can be taught in real-life, experiment treatment after completing teaching plan, post-GALT test, and paired sample t-test on the results of pre and post GALT in order. As a result, changes in the degree of logical thinking ability and in five sub-regions(conservative logic, proportional logic, combinatorial logic, probabilistic logic, controlling variables) composing of logical thinking obtained statistically significant results in .05 significance level but changes in the correlational logic couldn't obtain the significant results.

• Journal of the Korean Institute of Intelligent Systems
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• v.19 no.1
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• pp.13-18
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• 2009

Usually, human emotions are vague and change diversely on the basis of the stimulus from the outside. Plutchik classified the fundamental behavioral patterns into eight patterns, named each of them a genuine emotion, and furthermore suggested mixed emotions using a combination of genuine emotions. In this paper, we propose a method for processing Plutchik's emotion model using Multiple Valued Logic(MVL) Automata Model which utilizes the properties of difference in Multiple Valued Logic functions. This proposed emotion processing model can be widely applied to the analysis and processing of emotion data.

• Journal of the Korean Society of Earth Science Education
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• v.10 no.1
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• pp.17-25
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• 2017

The purpose of this study is to investigate the impact of logical thinking when applying STEAM program for middle school students. Therefore, you're creative, framework governing the conditions and be present, creative design of the emotional experience of class under the procedures of the program from a program by previous studies. STEAM improve program is entirely logical thinking to determine that 47 2nd grade in middle school student radio sampling four weeks, six round of poetry classes. Awareness stage after the program STEAM improved but there was little change in logical thinking and appears to be effective, particularly in conservation, combined logic.(p<0.05)

• Journal of the Korean Institute of Telematics and Electronics
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• v.12 no.4
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• pp.21-27
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• 1975

In this paper, a procedure for deriving of multiple fault detection test sets is presented for fan-out reconvergent combinational logic networks. A fan-out network is decomposed into a set of fan-out free subnetworks by breaking the internal fan-out points, and the minimal detecting test sets for each subnetwork are found separately. And then, the compatible tests amonng each test set are combined maximally into composite tests to generate primary input binary vectors. The technique for generating minimal test experiments which cover all the possible faults is illustrated in detail by examples.