• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.188-190
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• 2011

그리드는 지역적으로 분산된 이기종 컴퓨팅 자원을 하나의 가상 컴퓨팅 환경으로 통합하는 분산컴퓨팅 기술이다. 그러나, 그리드는 지리적으로 분산된 지역에 흩어져 있는 다양한 형태의 하드웨어 및 소프트웨어 자원을 포함하고 있기 때문에 자원의 이기종 특성은 그리드에 대한 자원 모니터링 및 자원 정보 수집을 어렵게 만든다. 한편, 그리드 환경에서 효율적인 자원할당과 QoS 를 보장하기 위해서는 먼저 각 자원의 사용 가능한 정도를 정확히 파악하여야 한다. 본 논문은 정확한 자원을 측정하기 위한 리소스 모니터링 시스템을 제안한다. 다양한 하드웨어 및 소프트웨어에 대한 실시간 자원 정보를 통합하고 이를 제공할 수 있는 분산 자원정보 및 모니터링 시스템을 설계 및 구현하였다.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.1
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• pp.173-180
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• 2022

Approximate Computing is a promising method for designing hardware-efficient computing systems. Approximate multiplication is one of key operations used in approximate computing methods for high performance and low power computing. An approximate 4-2 compressor can implement hardware-efficient circuits for approximate multiplication. In this paper, we propose an approximate multiplier with low area and low power characteristics. The proposed approximate multiplier architecture is segmented into three portions; an exact region, an approximate region, and a constant correction region. Partial product reduction in the approximation region are simplified using a new 4:2 approximate compressor, and the error due to approximation is compensated using a simple error correction scheme. Constant correction region uses a constant calculated with probabilistic analysis for reducing error. Experimental results of 8×8 multiplier show that the proposed design requires less area, and consumes less power than conventional 4-2 compressor-based approximate multiplier.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.1
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• pp.102-112
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• 2007

This paper includes an analysis of face recognition algorithm to design hardware and presents fixed point model in accordance with it. Face recognition algorithm detects the positions of face and eyes to make use of their feature data to detect and verify human faces. It distinguishes a particular user by means of comparing them with registered face features. To implement the face recognition algorithm into hardware, we developed its fixed point model by analyzing face feature parameters, face acquisition data, and feature detection parameters and operation structure.

• Journal of IKEEE
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• v.13 no.2
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• pp.253-259
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• 2009

In this paper, we propose a novel architecture of a general graphics shader processor without a dedicated hardware. Recently, mobile devices require the high performance graphics processor as well as the small size, low power. The proposed shader processor is a GP-GPU(General-Purpose computing on Graphics Processing Units) to execute the whole OpenGL ES 2.0 graphics pipeline by using shader instructions. It does not require the separate dedicate H/W such as rasterization on this fully programmable capability. The fully programmable 3D graphics shader processor can reduce much of the graphics hardware. The chip size of the designed shader processor is reduced 60% less than the sizes of previous processors.

• Journal of IKEEE
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• v.22 no.1
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• pp.104-109
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• 2018

This paper presents a hardware design for the block encryption algorithm of ARIA which is used for standard in Korea. It presents a hardware-efficient design to increase the throughput for the ARIA algorithm using a high-speed pipeline architecture. We have used ROM for the S-box implementation. This approach aims to decrease the critical path delay of the encryption. In this paper, hardware was designed by VHDL, realized RTL level by Synplify which is synthesis tool and verified simulation by ModelSim. The ARIA algorithm is shown 68.3 MHz (Maximum operation frequency) to use Xilinx VertxE XCV Series device.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.2
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• pp.7-15
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• 1983

In recent years, the logic circuits of high function have been developed to VLSI by the radical advancement of semi-conductor technologies. Under the above influence, it has become possible to design the special VLSI chips for high speed of numerical value processing, wide-band, image processing, etc. And, the development of the VLSI from various kinds of software package has become quite possible. This paper is to propose the technical skill of hardware design about general software package (BMD). The decrease of speed of former statistics processing caused by depending on software only is improved by hardware. In regard of design algorithm, the main system will be able to be established by considering of special feature of statistics. As a result, the complexity of software package is excluded by hardware. And, the efficiency is improved by high speed processing.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.138-144
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• 2013

In XRF systems, various techniques have been developed for the synthesis of pulse shapes using digital methods instead of traditional analog methods. Trapezoidal pulse shaping algorithms can be used for digital multi-channel pulse height analysis in X-ray spectrometer systems. In this paper, an efficient trapezoidal filter architecture is presented. In addition, we present a hardware-efficient peak value detection algorithm. By the proposed algorithm, peak value detection error is decreased by half compared with the conventional algorithm. The proposed Digital Pulse Processing(DPP) algorithm is designed using Verilog HDL and implemented using an FPGA on a test board. It is demonstrated that the implemented DPP board works successfully in practical XRF systems.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.2
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• pp.127-134
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• 2006

This paper describes a fully hardware realization of vector controller for the permanent magnet synchronous motor (PMSM) using high density field programmable gate mays (FPGA). In the proposed system, the vector controller including vector transformation , PI regulator, position and speed measurement, current measurement, and space vector PWM blocks is implemented in a FPGA using a VHSIC hardware description language (VHDL). The experimental results using a 1.1kW PMSM are provided to show the validity of the proposed system.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.5
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• pp.123-128
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• 2011

In this paper, we design the CA-CFAR processor using a root-square approximation approach and a fixed-point operation to improve hardware complexity and reduce computational effort. We also propose CA-CFAR processor with multi-window, which is capable of concurrent parallel processing. The proposed architecture is synthesized and implemented into the FPGA and the performance is compared with the conventional processor designed by root-square libarary licensed by FPGA corporation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.19-25
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• 2006

The fast processing ability of an RTOS (Real Time Operating System) is one of important factors in determining the performance of embedded systems. With the development of multimedia and telecommunication technology, the higher level of performance environments is required. Moreover there is some difficulty in improving the performance of an RTOS which is based on a microprocessor. In this paper, we propose a hardware architecture to implement some functions of uC/OS-II as a target RTOS for the purpose of its performance improvement. The proposed architecture for uC/OS-II is implemented and analyzed with the performance comparison.