• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.11
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• pp.140-149
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• 1996

Cursive characters are written on an economical principle to reduce the motion of a pen in the limit of distinction between characters. That is, the pen is not lifted up to move for writing a next stroke, the pen is not moved at all, or connected two strokes chance their shapes to a similar and simple shape which is easy to be written. For these reasons, strokes and korean alphabets are not only easy to be changed, but also difficult to be splitted. In this paper, we propose a curvature stroke modeling method for splitting and matching by using a structural primitive. A curvature stroke is defined as a substroke which does not change its curvanture. Input strokes handwritten in a cursive style are splitted into a sequence of curvature strokes by segmenting the points which change the direction of rotation, which occur a sudden change of direction, and which occur an excessive rotation Each reference of korean alphabets is handwritten in a printed style and is saved as a sequence of curvature strikes which is generated by splitting process. And merging process is used to generate various sequences of curvature strikes for matching. Here, it is also considered that imaginary strokes can be written or omitted. By using a curvature stroke as a unit of recognition, redundant splitting points in input characters are effectively reduced and exact matching is possible by generating a reference curvature stroke, which consists of the parts of adjacent two korean alphasbets, even when the connecting points between korean alphabets are not splitted. The results showed 83.6% as recognition rate of the first candidate and 0.99sec./character (CPU clock:66MHz) as processing time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).

• Journal of IKEEE
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• v.23 no.4
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• pp.1461-1464
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• 2019

In this paper, we propose the development of embedded board for integrated radiation exposure protection fireman's life-saving alarm capable of location tracking and radiation measurement. The proposed techniques consist of signal processing unit, communication unit, power unit, main control unit. Signal processing units apply shielding design, noise reduction technology and electromagnetic wave subtraction technology. The communication unit is designed to communicate using the wifi method. In the main control unit, power consumption is reduced to a minimum, and a high performance system is formed through small, high density and low heat generation. The proposed techniques are equipment operated by exposure to poor conditions, such as disaster and fire sites, so they are designed and manufactured for external appearance considering waterproof and thermal endurance. The proposed techniques were tested by an authorized testing agency to determine the effectiveness of embedded board. The waterproof grade has achieved the IP67 rating, which can maintain stable performance even when flooded with water at the disaster site due to the nature of the fireman's equipment. The operating temperature was measured in the range of -10℃ to 50℃ to cope with a wide range of environmental changes at the disaster site. The battery life was measured to be available 144 hours after a single charge to cope with emergency disasters such as a collapse accident. The maximum communication distance, including the PCB, was measured to operate at 54.2 meters, a range wider than the existing 50 meters, at a straight line with the command-and-control vehicle in the event of a disaster. Therefore, the effectiveness of embedded board for embedded board for integrated radiation exposure protection fireman's life-saving alarm has been demonstrated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• Journal of the Korean Society of Food Science and Nutrition
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• v.42 no.10
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• pp.1673-1681
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• 2013

Five different chopped frozen garlic products samples, three from Chinese and two from Korean origins being commercially available products in Korean market, were used to confirm their pre-pasteurization or pre-irradiation status by screening (direct epifluorescent filter technique/aerobic plate counts, DEFT/APC; electronic nose, E-nose; photostimulated luminescence, PSL) and identification (thermoluminescence, TL; electron spin resonance, ESR) techniques. Some parts of samples were gamma-irradiated at 1 kGy to be used as control samples in irradiation history identification. DEFT/APC and e-nose successfully showed distinct results between the domestic and imported samples. The PSL photon counts of all the unknown samples were less than 700 (negative), while most of 1 kGy-irradiated samples gave PSL photon counts more than 5,000 (positive). The domestic unknown samples produced the TL glow peaks after $300^{\circ}C$ or more, whereas the imported samples showed TL peaks at the range of $240{\sim}250^{\circ}C$. A clear TL glow peak was obtained from all irradiated samples at $150{\sim}250^{\circ}C$. The unknown samples of Chinese origin gave radiation-specific cellulose ESR signal that was not shown by domestic samples. A multiple step of applying the physical analytical methods is recommended for the effective identification of irradiation status on chopped frozen garlic products.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.

• Economic and Environmental Geology
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• v.34 no.1
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• pp.13-23
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• 2001

Bentonite layers are intercalated within the basal conglomerates in the Tertiary sedimentary basins of Kampo, Janggi and Pohang, southeastern Korea. Eighteen samples of the bentonites went through X-ray diffraction, scanning electron microscopy, heavy mineral analyses, chemical analyses and oxygen, hydrogen stable isotope analyses to define the mineralogical characters of the bentonites. Heavy minerals such as zircons, apatites, amphiboles and biotites separated from bentonites show clean and euhedral surfaces, which are the characteristic features of volcanic origin. But biotites from the Chunbook Conglomerate are found as altered and heavily broken flakes which implies longer transportation of these bentonites. $TiO_{2}/Al_{2}O_{3} ratios of <2 $\mu$m particle fractions (the Chunbook Conglomerate 0.031; Janggi 0.029; Kampo 0.025) suggest that those are originated from volcanic tuffs. That is, the higher the value is, the more mafic in chemical compositions of the original tuffs. Authigenic montmorillonite and zeolite minerals were observed by SEM, which indicates diagenesis origin of bentonites. But the samples from the Chunbook Conglomerate showed only chaotically packed clay flakes in the matrix of sands or conglomerates, which implies detrital influence, not authigenic origin. The structural formulae of montmorillonite from these basins reflects their environment of formation. Fe (Ⅵ) can show the redox condition of its past environment and much lower $Fe^{2+}(Ⅵ)/Fe^{3+}(Ⅵ)$ ratios in montmorillonite of the Chunbook Conglomerate imply the greater oxidizing influence. Calculated burial depths from oxygen stable isotope data of the samples from the Chunbook Conglomerate generally fall to the range of 929~963 m whereas the real burial depth of this area is only 530~580 m. This could be explained as the bentonites of the Chunbook conglomerate had not been formed in situ. Discriminant analyses with the data from chemical analyses and structural formulae of montmorillonites show that bentonites from three different basins could definitely be distinguished with each other. This result arises from the different chemical compositions of original volcanic ashes and the difference of sedimentary environments.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.