• Journal of Space Technology and Applications
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• v.3 no.4
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• pp.333-341
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• 2023

This study aims to develop technology for testing and verifying the space radiation environment of miniature space components using the facilities of the domestic 100 MeV proton accelerator and the Space Component Test Facility at the Space Testing Center. As advancements in space development progress, high-performance satellites increasingly rely on densely integrated circuits, particularly in core components components like memory. The application of semiconductor components in essential devices such as solar panels, optical sensors, and opto-electronics is also on the rise. To apply these technologies in space, it is imperative to undergo space environment testing, with the most critical aspect being the evaluation and testing of space components in high-energy radiation environments. Therefore, the Space Testing Center at the Korea testing laboratory has developed a radiation testing device for memory components and conducted radiation impact assessment tests using it. The investigation was carried out using 100 MeV protons at a low flux level achievable at the Gyeongju Proton Accelerator. Through these tests, single event upsets observed in memory semiconductor components were confirmed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.98-106
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• 2009

This work proposes a 1280-RGB $\times$ 800-Dot 70.78mW 0.l3um CMOS LCD driver IC (LDI) for high-performance 16M-color low temperature poly silicon (LTPS) thin film transistor liquid crystal display (TFT-LCD) systems such as ultra mobile PC (UMPC) and mobile applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed LDI optimizes power consumption and chip area at high resolution based on a resistor-string based architecture. The single column driver employing a 1:12 MUX architecture drives 12 channels simultaneously to minimize chip area. The implemented class-AB amplifier achieves a rail-to-rail operation with high gain and low power while minimizing the effect of offset and output deviations for high definition. The supply- and temperature-insensitive current reference is implemented on chip with a small number of MOS transistors. A slew enhancement technique applicable to next-generation source drivers, not implemented on this prototype chip, is proposed to reduce power consumption further. The prototype LDI implemented in a 0.13um CMOS technology demonstrates a measured settling time of source driver amplifiers within 1.016us and 1.072us during high-to-low and low-to-high transitions, respectively. The output voltage of source drivers shows a maximum deviation of 11mV. The LDI with an active die area of $12,203um{\times}1500um$ consumes 70.78mW at 1.5V/5.5V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.5 s.108
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• pp.461-475
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• 2006

In this paper, it is described about the tri-band mobile antenna system design to provide broadband multimedia and direct broadcasting services using goo-stationary Koreasat 3, simultaneously operated in Ka/K/Ku band. The radiating part of the antenna system with a fan beam characteristic in the elevation plane is composed of the quasi-offset dual shaped reflector and the tri-band feeder. The tri-band feeder is also composed of the Ka/K dual band feeder with the protruding dielectric rod, the circular polarizer, the ortho-mode transducer and the circular-polarized Ku band feed array. Especially, the Ka/K dual band circular polarizer was realized firstly using the comb-type structure. For fast satellite-tracking on the movement, the Ku band feed array has the structure of the $2{\times}2$ active phased array which can make electrical beams. And, the circular-polarized characteristic in the feed array was improved by $90^{\circ}$ rotating arrangement of four radiating elements polarized circularly by a $90^{\circ}$ hybrid coupler, respectively. Four beam forming channels to make electrical beams at Ku band are divided into the main beam channel and the tracking beam channel in the output, and noise temperature characteristics of each channel were analyzed on the basis of the contributions of internal sub_units. From the fabricated antenna system, the output power at $P_{1dBc}$ of Ka_Tx channel was measured more than 34.1 dBm and the measured noise figures of K/Ku_Rx channels were less than 2.4 dB and 1.5 dB, respectively, over the operating band. The radiation patterns with co- and cross-polarization in the tri-band were measured using a near-field measurement in the anechoic chamber. Especially, Ku radiation patterns were measured after correcting each initial phase of active channels with partial radiation patterns obtained from the independent excitation of each channel. The antenna gains measured in Ka/K/Ku band of the antenna system were more than 39.6 dBi, 37.5 dBi, 29.6 dBi, respectively. And, the antenna system showed good system performances such as Ka_Tx EIRP more than 43.7 dBW and K/Ku_Rx G/T more than 13.2 dB/K and 7.12 dB/K, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.21-28
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• 2017

Practical models for FPGA architectures which include performance- and/or density-enhancing components such as carry chains, wide function multiplexers, and memory/multiplier blocks are being applied to academic FPGA placement tools which used to rely on simple imaginary models. Previously the techniques such as pre-packing and multi-layer density analysis are proposed to remedy issues related to such practical models, and the wire length is effectively minimized during initial analytic placement. Since timing should be optimized rather than wire length, most previous work takes into account the timing constraints. However, instead of the initial analytic placement, the timing-driven techniques are mostly applied to subsequent steps such as placement legalization and iterative improvement. This paper incorporates the timing driven techniques, which check if the placement meets the timing constraints given in the standard SDC format, and minimize the detected violations, with the existing analytic placer which implements pre-packing and multi-layer density analysis. First of all, a static timing analyzer has been used to check the timing of the wire-length minimized placement results. In order to minimize the detected violations, a function to minimize the largest arrival time at end points is added to the objective function of the analytic placer. Since each clock has a different period, the function is proposed to be evaluated for each clock, and added to the objective function. Since this function can unnecessarily reduce the unviolated paths, a new function which calculates and minimizes the largest negative slack at end points is also proposed, and compared. Since the existing legalization which is non-timing driven is used before the timing analysis, any improvement on timing is entirely due to the functions added to the objective function. The experiments on twelve industrial examples show that the minimum arrival time function improves the worst negative slack by 15% on average whereas the minimum worst negative slack function improves the negative slacks by additional 6% on average.

• Journal of IKEEE
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• v.18 no.4
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• pp.552-558
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• 2014

This paper suggests how to design a ZigBee-chip-based communication module to remotely measure radiation level. The suggested communication module consists of two control processors for the chip as generally required to configure a ZigBee system, and one chip module to configure a ZigBee RF device. The ZigBee-chip-based communication module for remote radiation measurement consists of a wireless communication controller; sensor and high-voltage generator; charger and power supply circuit; wired communication part; and RF circuit and antenna. The wireless communication controller is to control wireless communication for ZigBee and to measure radiation level remotely. The sensor and high-voltage generator generates 500 V in two consecutive series to amplify and filter pulses of radiation detected by G-M Tube. The charger and power supply circuit part is to charge lithium-ion battery and supply power to one-chip processors. The wired communication part serves as a RS-485/422 interface to enable USB interface and wired remote communication for interfacing with PC and debugging. RF circuit and antenna applies an RLC passive component for chip antenna to configure BALUN and antenna impedance matching circuit, allowing wireless communication. After configuring the ZigBee-chip-based communication module, tests were conducted to measure radiation level remotely: data were successfully transmitted in 10-meter and 100-meter distances, measuring radiation level in a remote condition. The communication module allows an environment where radiation level can be remotely measured in an economically beneficial way as it not only consumes less electricity but also costs less. By securing linearity of a radiation measuring device and by minimizing the device itself, it is possible to set up an environment where radiation can be measured in a reliable manner, and radiation level is monitored real-time.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.321-322
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• 2012

의료용 방사선 장비는 초기의 아날로그 방식의 필름 및 카세트에서 진보되어 현재는 디지털 방식의 DR (Digital Radiography)이 널리 사용되며 그에 관한 연구개발이 활발히 진행되고 있다. DR은 크게 간접방식과 직접방식의 두 분류로 나눌 수 있는데, 간접방식은 X선을 흡수하면 가시광선으로 전환하는 형광체(Scintillator)를 사용하여 X선을 가시광선으로 전환하고, 이를 Photodiode와 같은 광소자로 전기적 신호로 변환하여 방사선을 검출하는 방식을 말하며, 직접 방식은 X선을 흡수하면 전기적 신호를 발생 시키는 광도전체(Photoconductor)를 사용하여 광도전체 양단 전극에 고전압을 인가한 형태를 취하고 있는 가운데, X선이 조사되면 일차적으로 광도전체 내부에서 전자-전공쌍(Electron-hole pair)이 생성된다. 이들은 광도전체 양단의 인가되어 있는 전기장에 의해 전자는 +극으로, 전공은 -극으로 이동하여 아래에 위치한 Active matrix array을 통해 방사선을 검출하는 방식이다. 본 연구에서는 직접방식 X-ray 검출기에서 활용되는 a-Se을 ITO (Indium Thin oxide) glass 상단에 Thermal evaporation증착을 이용하여 두께 $50{\mu}m$, 33 넓이로 증착 시킨 다음, a-Se상단에 Sputtering증착을 이용하여 ITO를 11 cm, 22 cm, $2.7{\times}2.7cm$ 넓이로 증착시켜 상하부의 ITO를 Electrode로 이용하여 직접방식의 X-ray검출기 샘플을 제작하였다. 제작 과정 중 a-Se의 Thermal evaporation증착 시, 저진공 $310^{-3}_{Torr}$, 고진공 $2.210^{-5}_{Torr}$에서 보트의 가열 온도를 두 번의 스텝으로 나누어 증착 시켰다. 첫 번째 스텝 $250^{\circ}C$, 두 번째 스텝은 $260^{\circ}C$의 조건으로 증착하여 보트 내의 a-Se을 남기지 않고 전량을 소모할 수 있었으며, 스텝간의 온도차를 $10^{\circ}C$로 제어하여 균일한 박막을 형성 할 수 있었다. Sputtering증착 시, 저진공 $2.510^{-3}$, 고진공 $310^{-5}$에서 Ar, $O_2$를 사용하여 100 Sec간 플라즈마를 생성시켜 ITO를 증착하였다. 제작된 방사선 각각의 검출기 샘플 양단의 ITO에 500V의 전압을 인가하고, 진단 방사선 범위의 70 kVp, 100 mA, 0.03 sec 조건으로 X-ray를 조사시켜 ITO넓이에 따른 민감도(Sensitivity)와 암전류(Dark current)를 측정하였다. 측정결과 민감도(Sensitivity)는 X-ray샘플의 두께에 따른 $1V/{\mu}m$ 기준 시, 증착된 ITO의 넓이가 11 cm부터 22 cm, $2.7{\times}2.7cm$까지 각각 $7.610nC/cm^2$, $8.169nC/cm^2$, $6.769nC/cm^2$로 22 cm 넓이의 샘플이 가장 높은 민감도를 나타내었으나, 암전류(Dark current)는 $1.68nA/cm^2$, $3.132nA/cm^2$, $5.117nA/cm^2$로 11 cm 넓이의 샘플이 가장 낮은 값을 나타내었다. 이러한 데이터를 SNR (Signal to Noise Ratio)로 합산 하였을 시 104.359 ($1{\times}1$), 60.376($2{\times}2$), 30.621 ($2.7{\times}2.7$)로 11 cm 샘플이 신호 대 별 가장 우수한 효율을 나타냄을 알 수 있었다. 따라서 ITO박막의 면적이 클수록 민감도는 우수하나 그에 따른 암전류의 증가로 효율이 떨어짐을 검증 할 수 있었으며, 이는 ITO면적이 넓어짐에 따른 저항의 증가로 암전류에 영향을 끼침을 할 수 있었다. 본 연구를 통해 a-Se의 ITO 박막 면적에 따른 전기적 특성을 검증할 수 있었다.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.4
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• pp.75-82
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• 2019

Flexible solar cells have attracted enormous attention in recent years due to their wide applications such as portable batteries, wearable devices, robotics, drones, and airplanes. In particular, the demands of the flexible silicon and compound semiconductor solar cells with high efficiency and high reliability keep increasing. In this study, we fabricated a flexible InGaP/GaAs double-junction solar module. Then, the effects of the wind speed and ambient temperature on the operating temperature of the solar cell were analyzed with the numerical simulation. The temperature distributions of the solar modules were analyzed for three different wind speeds of 0 m/s, 2.5 m/s, and 5 m/s, and two different ambient temperature conditions of 25℃ and 33℃. The flexibility of the flexible solar module was also evaluated with the bending tests and numerical bending simulation. When the wind speed was 0 m/s at 25 ℃, the maximum temperature of the solar cell was reached to be 149.7℃. When the wind speed was increased to 2.5 m/s, the temperature of the solar cell was reduced to 66.2℃. In case of the wind speed of 5 m/s, the temperature of the solar cell dropped sharply to 48.3℃. Ambient temperature also influenced the operating temperature of the solar cell. When the ambient temperature increased to 33℃ at 2.5 m/s, the temperature of the solar cell slightly increased to 74.2℃ indicating that the most important parameter affecting the temperature of the solar cell was heat dissipation due to wind speed. Since the maximum temperatures of the solar cell are lower than the glass transition temperatures of the materials used, the chances of thermal deformation and degradation of the module will be very low. The flexible solar module can be bent to a bending radius of 7 mm showing relatively good bending capability. Neutral plane analysis was also indicated that the flexibility of the solar module can be further improved by locating the solar cell in the neutral plane.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.1
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• pp.39-46
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• 2021

The quantitative measurement of interfacial adhesion energy (Gc) of multilayer thin films for Cu interconnects was investigated using a double cantilever beam (DCB) and 4-point bending (4-PB) test. In the case of a sample with Ta diffusion barrier applied, all Gc values measured by the DCB and 4-PB tests were higher than 5 J/㎡, which is the minimum criterion for Cu/low-k integration without delamination. However, in the case of the Ta/Cu sample, measured Gc value of the DCB test was lower than 5 J/㎡. All Gc values measured by the 4-PB test were higher than those of the DCB test. Measured Gc values increase with increasing phase angle, that is, 4-PB test higher than DCB test due to increasing plastic energy dissipation and roughness-related shielding effects, which matches well interfacial fracture mechanics theory. As a result of the 4-PB test, Ta/Cu and Cu/Ta interfaces measured Gc values were higher than 5 J/㎡, suggesting that Ta is considered to be applicable as a diffusion barrier and a capping layer for Cu interconnects. The 4-PB test method is recommended for quantitative adhesion energy measurement of the Cu interconnect interface because the thermal stress due to the difference in coefficient of thermal expansion and the delamination due to chemical mechanical polishing have a large effect of the mixing mode including shear stress.