• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.3
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• pp.784-794
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• 1996

In this papre, the design and the fabrication of the surface mountable voltage controlled oscillator is described for local oscillator in PCS(WACS/TDMA) handset. The VCO employs two silicon bipolar transistors of $f_{gamma}$ of 4 GHz as active devices. These are asembled to form the VCO on the 4 layer PCB of the size $12{\times}10mm$which provides the strip line resonator at the third layer. The fabricated VCO shows tuning rage over 50 MHz, phase noise -100 dBc/Hz at the 100 kHz frequency offset, and 0 dBm output power with the consumption of 22 mA at 3V. It is belived that the size will be more reduced by employing 1005 chip components and that the current consumption will be improved by employing transistors of higher $f_{gamma}$.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.235-244
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• 2000

This paper presents a low power PLL based clock geneator circuit for microprocessors. It generates 32MHz${\sim}$1GHz clocks and can be integrated inside microprocessor chips. A high speed D Flip-Flop is designed using dynamic differential latch and a new Phase Frequency Detector(PFD) based on this FF is presented. The PFD enjoys low error characteristics in phase sensitivity and the PLL using this PFD has a low phase error. To improve the linearity of voltage controlled oscillator(VCO) in PLL, the voltage to current converter and current controlled oscillator combination is suggested. The resulting PLL provides wide lock range and extends frequency of generated clocks over 1 GHz. The clock generator is designed by using $0.65\;{\mu}m$ CMOS full custom technology and operates with $11\;{\mu}s$ lock-in time. The power consumption is less than 20mW.

• Journal of Korea Multimedia Society
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• v.6 no.2
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• pp.325-331
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• 2003

In this paper, we designed a spiral inductor and voltage controlled oscillator with the negative resistor for the bluetooth receiver by using 0.25$\mu\textrm{m}$ 1-poly 5-metal CMOS n-well process. The proposed inductor, which applies multi layer metal structure, is a structure that decreases resistance value by increasing he metal thickness. As the resistance value decreases, the quality factor Q has improved. Also, voltage-controlled oscillator is designed applying 1 port negative resistance, and changes its oscillating frequency by varying outside capacitor values. The simulation results show that oscillating frequency is 2.33~2.58GHz changing from 2pF to 14pF, and the oscillator has oscillating power over 0dBm.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.4
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• pp.167-172
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• 2023

A low-noise phase-locked loop(PLL) with three negative feedback loops has been proposed. It is not easy to improve noise characteristics with a conventional PLL. The added negative feedback loops reduce the input voltage magnitude of voltage controlled oscillator which determines the jitter characteristics, enabling the improvement of noise characteristics. Simulation results show that the jitter characteristics are improved as a negative feedback loop is added. In the case of power consumption, it slightly rises by about 10%, but jitter characteristics are improved by about two times. The proposed PLL was simulated with Hspice using a 1.8V 180nm CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2480-2486
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• 2012

The design of low voltage LC-VCO(LC Voltage Controlled Oscillator) has been presented to optimize the phase noise and power consumption for the block of frequency synthesis to satisfy WCDMA system specification in this paper. The parameters for minimum phase noise has been obtained in the region of design, using the lines of the tuning range and the excess gain in the plane of the inductance and the transconductance of MOS transistor to compensate the loss of LC-tank. As a result of simulation, the phase noise characteristics is -113dBc/Hz for offset of 1MHz. The optimum designed LC-VCO has been fabricated using the process of 0.25um CMOS. As a result of measurement for fabricated chip, the phase noise characteristics is -116dBc/Hz for offset of 1MHz. The power consumption is 15mW, and Kvco is 370MHz/V.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.465-468
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• 2004

In this paper, we describe the design and implementation of the new current-current negative feedback (CCNF) voltage-controlled oscillator (VCO), which suppresses 1/f induced low-frequency noise. By means of the CCNF, the high-frequency noise as well as the low-frequency noise is prevented from being converted into phase noise. The proposed CCNF VCO shows 11-dB reduction in phase noise at 10 kHz offset, compared with the conventional differential VCO. The phase noise of the proposed VCO is -87 dBc/Hz at 10 kHz offset frequency from 5.5-GHz carrier. The proposed VCO consumes 14.0 mA at 2.0 V supply voltage, and shows single-ended output power of -12.0 dBm.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.9
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• pp.30-37
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• 2000

In this paper, design and fabrication of miniature voltage-controlled oscillator(VCO) is discussed . Based on the two-port circuit analysis technique, VCO for 900MHz cellular mobile phone is designed and circuit parameters are optimized using the circuit simulator. Using the optimized design parameters, miniature VCO with 6${\times}$6${\times}$1.8 mm$^3$(0.065cc) dimensions is fabricated and experimented. Experimental results show that implemented VCO has -3.5 dBm output power level and 45MHz tunung range, respectively, and has -101.5dB/Hz Phase noise performance at 10 KHz frequency offset.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.7
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• pp.649-656
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• 2002

This paper addresses the phase noise analysis of high-speed DH-PLL(Digital Hybrid Phase-Locked Loops) frequency synthesizer. Because of the additional quantization noise of D/A converter in DH-PLL, the phase noise of DH-PLL is increased than the conventional PLL. Three kinds of noise sources such as reference input, D/A converter, and VCO(Voltage Controlled Oscillator) are considered to analyze the phase noise. It largely depends on the closed loop bandwidth and frequency synthesis division ratio(N) so that we can decide the optimal closed loop bandwidth to minimize the phase noise of DH-PLL. It is shown that the simulation results closely match with the results of analytical approach.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.675-677
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• 2009

통신기기에서 중요한 기술 중 하나인 PLL(Phase Locked Loop) 회로는 주기적인 신호를 원하는 대로, 정확한 고정점으로 잡아주는데 그 목적을 둔다. 일반적인 구조로 위상주파수검출기(Phase Frequency detector), 루프필터(Loop filter), 전압제어발진기(Voltage Controlled Oscillator), 디바이더(Divider)로 구성되어진다. 그러나 일반적인 PLL 구조로는 지터(jitter)가 증가하고 트랙(tracking) 속도가 느리다는 단점이 있다. 이를 보완하기 위해 루프필터 전단에 차지펌프(Charge pump) 회로를 추가하여 사용하고 있다. 본 논문에서는 CMOS를 이용한 PLL용 차지펌프를 설계하였다. 설계된 회로는 $0.18{\mu}m$ CMOS 공정 기술을 사용하여 CADENCE사의 Specter로 시뮬레이션 하였으며, Virtuso2로 레이아웃 하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.690-692
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• 2009

PLL은 위상주파수검출기(PFD), 차지펌프(Charge Pump), 루프필터(Loop Filter), 전압제어발진기(VCO), Divider로 구성하고 있는데 본 논문에서는 설계된 차지펌프 PLL을 시뮬레이션을 해보고 그 결과를 정리하고 레이아웃(layout)까지 하였다. 차지펌프 설계에 있어서 전류 부정합, 전하 공유, 전하주입, 누설 전류등을 고려할 필요가 있다. 설계된 차지펌프는 전류 부정합을 감소시키기 위해 전류뺄셈회로를 이용하여 전류 부정합을 감소시켰으며, spurs를 억제할 수 있도록 설계되였다. 설계된 회로는 $0.18{\mu}m$ CMOS 공정 기술을 사용하여 CADENCE사의 specter로 시뮬레이션 하였으며, virtuso2로 레이아웃 하였다.