• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.8
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• pp.47-52
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• 2010

In this paper, a phase-locked loop with a self-noise suppressing voltage controlled oscillator to improve a phase noise characteristic has been proposed. The magnitude of the proposed transfer function is maximum 25dB lower than that of a conventional transfer function around a bandwidth. The proposed PLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.760-761
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• 2013

본 논문은 차량 추돌 예방 레이더용 24GHz 전압제어발진기를 제안한다. 이러한 회로는 TSMC $0.13{\mu}m$ 혼성신호/고주파 CMOS 공정($f_T/f_{MAX}=120/140GHz$)으로 설계되어 있다. 이러한 회로는 스위치형 공진기 (switched resonator)의 기본 구조를 지닌 24GHz 주파수 대역을 사용할 수 있도록 CMOS LC 튜닝 회로를 포함하고 있다. 특히 전체 칩 면적을 줄이기 위해 수동형 인덕터 대신 능동형 인덕터부를 사용하였다. 본 연구에서 개발한 발진기는 전체 튜닝 범위에 대해 24GHz에서 8%의 측정결과를 보였으며, 600kHz 오프셋에서 24GHz에 대해 약 -89dBc/Hz의 우수한 위상 잡음 특성을 보였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.702-703
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• 2013

본 논문은 차량 추돌 예방 레이더용 24GHz 전압제어발진기를 제안한다. 이러한 회로는 TSMC $0.13{\mu}m$ 혼성신호/고주파 CMOS 공정($f_T/f_{MAX}=120/140GHz$)으로 설계되어 있다. 이러한 회로는 스위치형 공진기 (switched resonator)의 기본 구조를 지닌 24GHz 주파수 대역을 사용할 수 있도록 CMOS LC 튜닝 회로를 포함하고 있다. 특히 전체 칩 면적을 줄이기 위해 수동형 인덕터 대신 능동형 인덕터부를 사용하였다. 본 연구에서 개발한 발진기는 전체 튜닝 범위에 대해 24GHz에서 8%의 측정 결과를 보였으며, 600kHz 오프셋에서 24GHz에 대해 약 -89dBc/Hz의 우수한 위상 잡음 특성을 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.72-78
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• 2009

This paper proposes a low phase noise ring voltage controlled oscillator(VCO) with a standard $0.13{\mu}m$ CMOS process for PLL circuit using the VCO-gain-controlled Delay cell. The proposed Delay cell architecture with a active resistor using a MOS transistor. This method can reduced a VCO gain so that improve phase noise. And, Delay cell consist of Wide-Swing Cascode current mirror, Positive Latch and Symmetric load for low phase noise. The measurement results demonstrate that the phase noise is -119dBc/Hz at 1MHz offset from 1.9GHz. The VCO gain and power dissipation are 440MHz/V and 9mW, respectively.

• Journal of IKEEE
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• v.17 no.1
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• pp.16-21
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• 2013

Recently, frequency synthesizers are being designed in two ways narrow-band loop or dual-loop for wide-band to reduce the phase noise. However, dual-loop has the disadvantage of center frequency mismatch and requiring an extra loop. In this paper, we propose a new structure that supports a range of 800Mhz ~ 3Ghz with multiple control of the single-loop frequency synthesizer without another loop. The control voltage of the VCO(coarse, fine) will be fixed, and finally the VCO will have a low Kvco. The frequency synthesizer is simulated using UMC $0.11{\mu}m$ process, proposed frequency synthesizer can be used in a variety of applications in the future.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.9 no.6
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• pp.843-849
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• 1998

A voltage controlled oscillator using dielectric resonator for 2.4 GHz WLL System is designed and fabricated. To improve the phase noise characteristic resonator is used as an inductor of VCO. At the bias condition of 5 V and 10 mA, the output power and phase noise in the operating frequency range of 2210~2240 MHz are 0 dBm and 100 dBc/Hz 10 kHz offset from the carrier, respectively. The phase noise and harmonic response of fabricated VCO are suitable for WLL system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.301-306
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• 2005

In this paper, a gain-boosting charge pump(CP) and a latch type voltage controlled oscillato.(VCO) with voltage controlled resistor(VCR) were proposed. The gain-boosting CP achieves good .current matching of less than 11$mu$V voltage difference between 43$mu$V and 32$mu$V in its output range from 0.8V to 2.3V. The VCO with VCR shows good linear characteristics over the range from 1V to 3V. The fabricated VCO exhibits -108dBc/Hz phase noise at a 100kHz and is comparable to that of the integrated LC-tank oscillator. The phase locked loop(PLL) with new circuits was simulated in a 0.35$mu$m CMOS process and showed 150$mu$s locking time.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.6
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• pp.570-579
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• 2009

In this paper, we presented a Vt-DRO with a wide electrical frequency tuning range, using open-loop gain method. The Vt-DRO was composed of 3-stages, resonator, amplifier and phase shifter. In order to satisfy an oscillation condition, we determined magnitude and phase of each stage. The measured S-parameter of cascaded 3-stages shows open-loop oscillation condition. Also, using measured open loop group delay, we derived the relation for electrical frequency tuning range. The Vt-DRO was implemented by connecting the input and the output of the designed open-loop and resulted in closed-loop. As a results, tuning-range of Vt-DRO is 82 MHz, which is close to the predicted results for tuning voltage 0${\sim}$10 V and shows linear frequency tuning at the center frequency of 5.3 GHz. The phase noise is -104 ${\pm}$1 dBc/Hz at 100 kHz offset frequency and power is 5.86${\pm}$1 dBm respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.74-80
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• 2009

This paper describes a $2{\sim}6GHz$ CMOS frequency synthesizer that employs only one LC-tank voltage controlled oscillator (VCO). For wide-band operation, optimized LO signal generator is used. The LC-tank VCO oscillating in $6{\sim}8GHz$ provides the required LO frequency by dividing and mixing the VCO output clocks appropriately. The frequency synthesizer is based on a fractional-N phase locked loop (PLL) employing third-order 1-1-1 MASH type sigma-delta modulator. Implemented in a $0.18{\mu}m$ CMOS technology, the frequency synthesizer occupies the area of $0.92mm^2$ with of-chip loop filter and consumes 36mW from a 1.8V supply. The PLL is completed in less than $8{\mu}s$. The phase noise is -110dBC/Hz at 1MHz offset from the carrier.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.3
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• pp.283-289
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• 2018

A PLL with an unipolar charge pump and a loop filter consisting of sample-hold capacitor and Fvco-sampled feedforward loop filter. The proposed PLL not only reduces the chip area by replacing the resistance to a switch and a small capacitor but also reduces the variation of ${\Delta}VLPF$ and ${\Delta}{\Delta}VLPF$ to 1/6 and 1/5 respectively. The variation of ${\Delta}VLPF$ is related to the phase noise of VCO output and that of ${\Delta}{\Delta}VLPF$ is proportional to reference spurs. It has been simulated and verified with a 1.8V $0.18{\mu}m$ CMOS process and shown a good phase noise characteristics. We plan to fabricate chip based on the simulations and check performance.