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http://dx.doi.org/10.7471/ikeee.2013.17.1.016

A Design of PLL for 6 Gbps Transmitter in Display Interface Application  

Yu, Byeong-Jae (DOESTEK Co., Ltd.)
Cho, Hyun-Mook (School of Electrical, Electronics, and Control Engineering, Kongju University)
Publication Information
Journal of IKEEE / v.17, no.1, 2013 , pp. 16-21 More about this Journal
Abstract
Recently, frequency synthesizers are being designed in two ways narrow-band loop or dual-loop for wide-band to reduce the phase noise. However, dual-loop has the disadvantage of center frequency mismatch and requiring an extra loop. In this paper, we propose a new structure that supports a range of 800Mhz ~ 3Ghz with multiple control of the single-loop frequency synthesizer without another loop. The control voltage of the VCO(coarse, fine) will be fixed, and finally the VCO will have a low Kvco. The frequency synthesizer is simulated using UMC $0.11{\mu}m$ process, proposed frequency synthesizer can be used in a variety of applications in the future.
Keywords
frequency synthesizers; PLL; dual loop; wide band; Transmitter;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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