• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.673-676
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• 2015

Digital Pre-Distortion (DPD) is a linearization technique for nonlinear power amplifiers (PAs) by implementing inverse function of the PA at baseband digital stage. To obtain proper DPD parameters, a feedback path is required to convert the PA output to a baseband signal, and a memory is also needed to store the feedback signals. DPD parameters are usually found by an adaptive algorithm from the feedback samples. However, for the adaptive algorithm to converge to a reliable solution, long feedback samples are required, which increases convergence time and hardware complexity. In this paper, we propose a DPD technique that requires relatively short feedback samples. From the observation that the convergence time of the adaptive algorithm highly depends on the initial condition, this paper iteratively utilizes the feedback samples while keeping and using the converged DPD parameters at the former iteration as the initial condition at the current iteration. Computer simulation results show that the proposed method performs better than the conventional technique while the former requires much shorter feedback samples than the latter.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.1
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• pp.115-119
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• 2008

In this paper, the linearity of Doherty power amplifier has been improved by applying a new Photonic Bandgap(PBG) structure on the output of amplifier. The reposed spiral PBG structure is a two-dimensional(2-D) periodic lattice patterned on a dielectric slab that does not require nonplanar fabrication process. This structure has more broad stopband and high suppression performance than the conventional three cell PBG. Also, It has a sharp skirt property. We obtained the 3rd-order intermodulation distortion(IMD3) of -33dBc for CDMA applications with that of maintaining the constant power added efficiency(PAE), the IMD3 performance is improved as much as -8 dB compared with a Doherty power amplifier without PBG structure. Moreover, the physical length of PBG is shortened, therefore the whole amplifier circuit size is considerably reduced.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.7 no.1
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• pp.53-60
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• 1996

The 8W hybrid MIC SSPA has been developed in the frequency range from 14.0 GHz to 14.5 GHz for uplink of KOREASAT's earth station. The whole system was designed of two parts with driving amplifier and high power amplifier to simplify the fabrication process. we reduced weight and volum of power amplifier through arranging the bias circuits in the same housing. The realized SSPA has a small signal gain of $26\pm1dB$within 500 MHz bandwidith, and the input and output return losses are over 7dB and 12dB respectively. The output power of 39.0 ~ 39.2dBm is achieved at the 1dB gain compression point of 14 GHz, 14.25 GHz, and 14.5 GHz. That reveals higher power than 8W of design target. The proposed SSPA manufacture techni- ques in this paper can be applied to the implementation of power amplifiers for some radars and SCPC.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.9
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• pp.1065-1071
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• 2010

In this paper, we proposed a novel harmonic load circuit to design a high efficiency class-F amplifier. The proposed load circuit controls termination impedances to enhance the efficiency of class-F power amplifier. The termination impedances at the 2nd and the 3rd harmonics are showed short and open condition, respectively. Also, a fabricated load circuit showed an attenuation characteristic more than 29 dB, that is enough to eliminate harmonics of the class-F power amplifier. The measured drain and power-added efficiency are 75.7 % and 71.3 % at the point of maximum output power 35.17 dBm.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2003.05a
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• pp.92-96
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• 2003

In this paper, 30 W power Amplifier for IMT-2000 repeater was developed gain flatness and the third IMD (Intermodulation distortion) by Microwave absorber. The absorption ability of the absorber is measured up to -10 ㏈ and -4 ㏈ at 3.6 ㎓, 2.3 ㎓ band respectively. Non using absorber power amplifier has the gain over 57 ㏈, the gain flatness of ${\pm}$0.33 ㏈ and the third IMD of 27 ㏈c at 33.3 W output. Otherwise, using absorber power amplifier has the gain over 58㏈, the gain flatness of less than ${\pm}$0.9, the third IMD over 29 ㏈c at the same output power. As a result, the characteristic of the different type show improvement of 1 ㏈ in gain, 0.3 ㏈ in Gain flatness and 1.77 ㏈c in IMD.

• Journal of Advanced Navigation Technology
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• v.27 no.6
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• pp.849-854
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• 2023

In this paper, a high-efficiency power amplifier was designed by applying the operating point Class J using LDMOS(laterally diffused metal oxide semiconductor) and optimizing the output matching circuit so that the second harmonic impedance becomes the reactance impedance. The designed power amplifier has a frequency of 108 ~ 110 MHz, Characteristics of PAE(power added efficiency) is 71.5% at P_SAT output (54.5 dBm), 55.5% at P_1dB output (51.5 dBm), and 24.38% at 45 dBm. The CSB(carrier with sideband) amplifier, which is the reference signal in the spatial modulation method, has an operating output of 45 dBm ~ 35 dBm, and linear SDM(sum in the depth of modulation) characteristics(40% ± 0.3%) were obtained. We measure the characteristics in amplitude modulation according to the bias operating point of the power amplifier for CSB and propose the optimal operating point to obtain linear modulation characteristics.

• Journal of IKEEE
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• v.25 no.1
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• pp.133-138
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• 2021

We propose a Ku-band three-stack CMOS power amplifier to enhance the output power and efficiency. To minimize the dc power consumption, the driver stage is designed using common-source structure. To obtain high output power and utilize a voltage combining method, the power stage is designed using stack structure. To verify the proposed power amplifier structure, we design a Ku-band power amplifier using 65-nm RFCMOS process which provide nine metal layers. The P1dB, power-added efficiency, and gain are higher than 20 dBm, 23 dB, and 25%, respectively, while the operating frequency is 14 GHz-16 GHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.902-911
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• 2003

Using InGaP/GaAs HBT power cells with a 2.0${\times}$20$\mu\textrm{m}$$^2$ emitter area of a unit HBT, a two stage MMIC power amplifier has been developed for IMT-2000 handsets. An active-bias circuit has been used for temperature compensation and reduction in the idling current. Fitting on measured S-parameters of the HBT cells, circuit elements of HBT's nonlinear equivalent model have been extracted. The matching circuits have been designed basically with the extracted model. A two stage HBT MMIC power amplifier fabricated using ETRI's HBT process. The power amplifier produces an 1-㏈ compressed output power(P$\_$l-㏈/) of 28.4 ㏈m with 31% power added efficiency(PAE) and 23-㏈ power gain at 1.95 GHz in on-wafer measurement. Also, the power amplifier produces a 26 ㏈m output power, 28% PAE and a 22.3-㏈ power gain with a -40 ㏈c ACPR at a 3.84 ㎒ off-center frequency in COB measurement.quency in COB measurement.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.5
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• pp.521-524
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• 2015

This letter presents a selective wireless power transfer architecture using a reconfigurable multi-port amplifier. The proposed wireless power transfer architecture is composed of a phase shifter part controlled by FPGA, two class-E power amplifiers, a four-port power combiner and two coil loads. Depending on the phase control of FPGA, the power ratio of outputs at the two coil loads becomes 1:1, 2:0 and 0:2. The manufactured system has delivered 1W DC power to loads at 125 kHz. The total DC-to-DC conversion efficiency shows more than 40 % including PA efficiency of 79 %.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.9
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• pp.895-902
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• 2014

This paper presents a 2-stage CMOS power amplifier for the 1.75 GHz band using a $0.18-{\mu}m$ CMOS process. Using ADS simulation, a power gain of 28 dB and an efficiency of 45 % at an 1dB compression point of 27 dBm were achieved. The implemented CMOS power amplifier delivered an output power of up to 24.8 dBm with a power-added efficiency of 41.3 % and a power gain of 22.9 dB. For a 16-QAM uplink LTE signal, the PA exhibited a power gain of 22.6 dB and an average output power of 23.1 dBm with a PAE of 35.1 % while meeting an ACLR(Adjacent Channel Leakage Ratio) level of -30 dBc.