• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.05b
• /
• pp.31-34
• /
• 2003

The sapphire wafers for blue light emitting devices were manufactured by the implementation of the surface machining technology based on micro-tribology. This process has been performed by chemical and mechanical polishing(CMP) process. The sapphire crystalline wafers were characterized by double crystal X-ray diffraction. The sample quality of sapphire crystalline wafer at surfaces has a full width at half maximum 89 arcses. The surfaces of sapphire wafers were mechanically affected by residual stress and surface default. Sapphire wafers's waveness has higher abrasion rate in the edge of the wafer than its center due to Newton's Ring interference.

• Journal of IKEEE
• /
• v.19 no.1
• /
• pp.41-44
• /
• 2015

Silicon trench process for bulk fin field effect transistor (finFET) is suggested without using chemical mechanical polishing (CMP) that cause contamination problems with chemical stuff. This process uses thickness difference of photo resistor spin coating and silicon nitride sacrificial layer. Planarization of silicon oxide and silicon trench formation can be performed with etching processes. In this work 50 nm silicon trench is fabricated with AZ 1512 photo resistor and process results are introduced.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.11a
• /
• pp.112-112
• /
• 2008

박막형 태양전지에 관한 연구는 1954년 D.C. Reynolds 가 단결정 CdS 에서 광기전력을 발견하면서부터 시작되었다. 고효율 단결정 규소 태양전지가 간편하게 제작되고 박막형 태양전지의 수명문제가 대두되어 한때는 연구가 중단되어지기도 하였으나, 에너지 문제가 심각해지면서 값이 저렴하고 넓은 면적에 쉽게 실용화 할 수 있는 박막형 태양전지에 많은 관심을 가지게 되었다. 박막형 태양전지에 사용되는 CdS는 II-VI 족 화합물 반도체로서 에너지금지대폭이 2.42eV인 직접천이형 n-type 반도체로서 대부분의 태양광을 통과시킬 수 있으며 가시광선을 잘 투과시키고 낮은 비저항으로서 광흡수층인 CdTe/$CuInSe_2$ 등과 같이 태양전지의 광투과층(윈도레이어)으로 널리 사용되고 있다. 이러한 이종접합 박막형 태양전지의 효율을 높이기 위해선 윈도레이어 재료인 CdS 박막의 낮은 전기 비저항치와 높은 광 투과도 값이 요구되어지고 있다. CdS 박막의 제작방법으로는 spray pyrolysis법, 스크린프린팅, 소결법, puttering법, 전착법, CBD(chemical bath deposition)법 및 진공증착법 등의 여러 가지 방법들이 보고되었다. 이 중 sputtering의 경우, 다른 방법들에서는 얻기 어려운 매우 얇은 두께의 박막 증착이 가능하며, 균일성 또한 우수하다. 또한 대면적화가 용이하여 양산화 기술로는 다른 제조 방법들에 비해 많은 장점을 가지고 있다. 따라서 본 연구에서는 sputtering에 의해 증착한 CdS의 박막에 광투과도 등의 향상을 위하여 CMP( chemical mechanical polishing) 공정을 적용하여 표면 특성을 개선하고자 하였다. 그 기초적인 자료로서 CdS 박막의 CMP 공정 조건에 따른 연마율과 비균일도, 표면 특성 등을 ellipsometer, AFM(atomic force microscopy) 및 SEM(scanning electron microscope) 등을 활용 하여 분석하였다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.1
• /
• pp.127-132
• /
• 2012

In this paper, the edge effects of proposed structure in active region for high voltage in shallow trench isolation for very large integrated MOSFET were simulated. Shallow trench isolation (STI) is a key process component in CMOS technologies because it provides electrical isolation between transistors and transistors. As a simulation results, shallow trench structure were intended to be electric functions of passive, as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage.

• Journal of the Korea Society for Simulation
• /
• v.22 no.4
• /
• pp.93-98
• /
• 2013

In this paper, the proposed shallow trench isolation structures for high threshold voltage for very large scale and ultra high voltage integrated circuits MOSFET were simulated. Physically based models of hot-carrier stress and dielectric enhanced field of thermal damage have been incorporated into a TCAD tool with the aim of investigating the electrical degradation in integrated devices over an extended range of stress biases and ambient temperatures. As a simulation results, shallow trench structure were intended to be electric functions of passive, as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.121-122
• /
• 2008

Lithium Niobate (LN:LiNbO3) is a compound of niobium, lithium and oxygen. The characteristics of LN are piezoelectricity, ferroelectricity and photoelectricity, and which is widely used in surface acoustic wave (SAW). To manufacture LN device, the LN surface should be a smooth surface and defect-free because of optical property, but the LN material is processed difficult by traditional processes such as grinding and mechanical polishing (MP) because of its brittleness. To decrease defects, chemical mechanical polishing (CMP) was applied to the LN wafer. In this study, the suitable parameters scuh as pressure and relative velocity, were investigated for the LN CMP process. To improve roughness, the LN CMP was performed using the parameters that were the highest removal rate among process parameters. And, evaluation of optical property was performed by the optical reflectance and non-linear characteristic.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.37 no.3
• /
• pp.319-324
• /
• 2013

In this study, an EP (electro-polishing)-MAP (magnetic abrasive polishing) hybrid process was developed as a precision finishing process. To evaluate the characteristics of this EP-MAP hybrid process, a series of experiments were carried out using various working gaps, current densities, and electrolyte concentrations. As a result, $NaNO_3$ was found to be very suitable as the electrolyte of the hybrid process because there was no electrochemical reaction with the CNT-Co composite. Moreover, an increase in the magnetic flux density affected the liquidity of the electrolyte and prevented it from flowing into the CNT-Co composite powder. For that reason, the lower liquidity of the electrolyte increased the thermal energy on the surface of the workpiece.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.141-141
• /
• 2009

Blue light-emitting diodes (LEDs), violet laser diodes 같은 광전소자들은 질화물 c-plane 기판위에 소자로 응용되어 이미 상품화 되어 왔다. 그러나 2족-질화물 재료들은 wurtzite 구조를 가지므로 c-plane에 평행한 자연적인 극성을 띌 뿐만 아니라 결정 내부 stress로 인한 압전현상 또한 나타나 큰 내부 전기장을 형성하게 된다. 이렇게 생성된 내부 전기장은 전자와 홀의 재결합 효율을 감소시키고 소자 응용 시 red-shift의 원인이 되곤 한다. 따라서 최근 들어 m-plane(1-100), a-plane (11-20)같은 무극성을 뛰는 기판 위에 소자를 만드는 방법이 각광을 받고 있는 추세다. 그러나 무극성 기판을 소자에 응용 시 Chemical Mechanical Planarization (CMP)에 의한 가공은 반도체 기판으로써 이용하기 위한 필수 불가결의 공정이다. c면(0001) SiC wafer에 대한 연구는 현재 많이 발표가 되어 있으나 무극성면 SiC wafer에 대한 CMP 공정에 대한 연구사례는 없는 실정이다. 본 연구에서는 C면 (0001)으로 성장된 잉곳을 a면(11-20)과 m(1-100)면으로 절단 후, slurry type (KOH-based colloidal silica slurry, NaOCl), 산화제, 연마제등을 변화하여 CMP 공정을 거침으로서 일어나는 기계 화학적 가공 양상에 대하여 알아보았다. 그 후 표면 형상 분석 하기위해 Atomic Force Microscope(AFM)을 사용하였고, 표면 스크레치를 SEM을 이용해서 알아보았다.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.6
• /
• pp.1146-1150
• /
• 2009

Cadmium telluride (CdTe) is one of the most attractive photovoltaic materials due to its low cost, high efficiency and stable performance in physical, optical and electronic properties. Few researches on the influences of uniform surface on the photovoltaic characteristics in large-area CdTe solar cell were not reported. As the preceding study of the effects of thickness-uniformity on the photovoltaic characteristics for the large-area CdTe thin film solar cell, chemical mechanical polishing (CMP) process was investigated for an enhancement of thickness-uniformity. Removal rate of CdTe thin film was 3160 nm/min of the maximum value at the 200 $gf/cm^2$ of down force (pressure) and 60 rpm of table speed (velocity). The removal rate of CdTe thin film was more affected by the down force than the table speed which is the two main factors directly influencing on the removal rate in CMP process. RMS roughness and peak-to-valley roughness of CdTe thin film after CMP process were improved to 96.68% and 85.55%, respectively. The optimum process condition was estimated by 100 $gf/cm^2$ of down force and 60 rpm of table speed with the consideration of good removal uniformity about 5.0% as well as excellent surface roughness for the large-area CdTe solar cell.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.53 no.3
• /
• pp.128-132
• /
• 2004

The perovskite ferroelectric materials of the PZT, SBT and BST series will attract much attention for application to ULSI devices. Among these materials, the BST ($Ba_0.6$$Sr_0.4$/$TiO_3$) is widely considered the most promising for use as an insulator in the capacitors of DRAMS beyond 1 Gbit and high density FRAMS. Especially, BST thin films have a good thermal-chemical stability, insulating effect and variety of Phases. However, BST thin films have problems of the aging effect and mismatch between the BST thin film and electrode. Also, due to the high defect density and surface roughness at grain boundarys and in the grains, which degrades the device performances. In order to overcome these weakness, we first applied the chemical mechanical polishing (CMP) process to the polishing of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. BST ferroelectric film was fabricated by the sol-gel method. And then, we compared the surface characteristics before and after CMP process of BST films. We expect that our results will be useful promise of global planarization for FRAM application in the near future.