• 제목/요약/키워드: 저전력 모드

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A New Logic Transformation Method for Both Low Power and High Testability (저 전력소모와 높은 테스트용이성을 위한 새로운 논리 변환 방법)

  • 손윤식;정정화
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.9
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    • pp.692-701
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    • 2003
  • In this paper, a new logic transformation method to consider both low power consumption and high testability is proposed. We search the CFF(Compact Fanout Free) that has low probability of being observable at the primary outputs. Under the condition that the CFF is unobservable at all primary outputs, the switching operations in it can be removed by adding redundant connections into it. The testability of the transformed circuit generally tends to reduce. In our method, however, the inserted redundant connections operate as test points in the test mode and can improve not only the controllability but also the observability of the CFF. The transformed circuit consumes less power in the normal mode and also has higher testability in the test mode. To show the efficiency of the proposed logic transformation method, we perform some experiments on the MCNC benchmark test circuits. The results show that the power consumption of the transformed circuit is reduced by 13% maximally and the fault coverage of the transformed circuit is increased.

Design and Implementation of OFDM Frequency Offset Synchronization Block Using CORDIC (CORDIC을 이용한 OFDM 주파수 옵셋 동기부 설계 및 구현)

  • Jang, Young-Beom;Han, Jae-Woong;Hong, Dae-Ki
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.45 no.5
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    • pp.118-125
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    • 2008
  • In this paper, an efficient frequency offset synchronization structure for OFDM(Orthogonal Frequency Division Multiplexing) is proposed. Conventional CORDIC(Coordinate Rotation Digital Computer) algorithm for frequency offset synchronization utilizes two CORDIC hardware i.e., one is vector mode for phase estimation, the other is rotation mode for compensation. But proposed structure utilizes one CORDIC hardware and divider. Through simulation, it is shown that hardware implementation complexity is reduced compared with conventional structures. The Verilog-HDL coding and front-end chip implementation results for the proposed structure show 22.1% gate count reduction comparison with those of the conventional structure.

A operation scheme to the power consumption of base station in wireless networks (무선망에서 기지국의 전력소모에 대한 운영 방안)

  • Park, Sangjoon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.24 no.2
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    • pp.285-289
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    • 2020
  • The configuration of hierarchical wireless networks is provided to support diverse network environments. In the base station, two system state can be basically considered for the operation management so that the state transition may be occurred between active and sleep modes. Hence, to reduce energy consumption the system operation management of the low power should be considered to the base station system. In this paper we consider the analytical model of Discontinuous Reception (DRX) to investigate the system management. We provide the analysis scheme of base station system by the DRX model, and the low power factor would be investigated for the energy consumption. We also use the finite-state Markov system model that in a system state period the wireless resource request and the operation of service call arrival interval is considered to numerically analyze the performance of energy saving operations of base station.

A NAV-based Power Management in IEEE 802.11 Networks (IEEE 802.11에서 NAV에 기반한 전력 관리 기법)

  • 윤상식;차호정
    • Proceedings of the Korean Information Science Society Conference
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    • 2004.04a
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    • pp.523-525
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    • 2004
  • 무선 단말은 제한된 배터리로 동작하는 특성을 가지기 때문에 에너지 효율성은 중요한 과제로 남아있다. 본 논문에서는 IEEE 802.11 MAC 프로토콜의 Network Allocation Vector(NAV)에 기반한 전력관리기법을 제안한다. NAV는 매체점유시간에 대한 정보를 제공하기 때문에 WNIC가 저 전력 모드로 동작할 수 있는 지표가 된다. 또한 Throughput과 WNIC의 상태 전이에 요구되는 오버헤드를 정량적으로 고려함으로써 에너지 효율성을 극대화한다. 제안된 기법은 ns-2를 이용하여 성능 분석하였고, 일정한 전송률을 보이는 응용에서 성능향상을 보임을 알 수 있다.

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AC/DC Pulse-Resonant Converter with Synchronous Rectifier (동기정류기를 이용한 펄스공진형 AC/DC 컨버터)

  • Chung, Gyo-Bum
    • Proceedings of the KIPE Conference
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    • 2005.07a
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    • pp.113-115
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    • 2005
  • 본 연구는 저전압 교류 전류원으로부터 직류 부하에 에너지를 공급하기 위하여, 새로운 컨버터를 제안한다. 컨버터는 풀브리지 MOSFET 정류기와 플라이백 컨버터의 2단 구조로 구성되어 있으며, LC공진을 이용하여 AC/DC 전력변환을 수행한다. 컨버터 효율 개선을 위하여 컨버터 회로 내의 스위칭 소자는 3상한에서 동작한다. 제안된 컨버터의 동작원리 및 동작모드를 해석하고, 시뮬레이션을 통해 해석결과를 검증하였다.

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Design and Implementation of Low-Power Object-based IP Storage for Mobile Devices using WLAN Power Control (WLAN 전력제어를 적용한 모바일 단말용 저전력 객체기반 IP 스토리지 설계 및 구현)

  • Nam, Young-Jin;Choi, Min-Seok;Jeon, Young-Joon;Ryu, Jeong-Tak;Moon, Byung-Hyun
    • Journal of Korea Society of Industrial Information Systems
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    • v.12 no.4
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    • pp.32-40
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    • 2007
  • A mobile device accesses large-sized data in object-based IP storage as an object unit over IP network. It relies heavily on a WLAN device, which has been known as one of the major power consumers. This paper designs and implements low-power object-based IP storage for mobile devices using an efficient WLAN power control. The proposed WLAN power control exploits prefetch buffer to maximize the idleness for incoming network traffic and controls available WLAN power modes to minimize the power consumption. Our experimental results reveal that the proposed WLAN control can save the total power consumption in a PXA270-based mobile device about 9% while playing the multimedia contents through an object-based IP storage device

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A 13-Gbps Low-swing Low-power Near-ground Signaling Transceiver (13-Gbps 저스윙 저전력 니어-그라운드 시그널링 트랜시버)

  • Ku, Jahyun;Bae, Bongho;Kim, Jongsun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.4
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    • pp.49-58
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    • 2014
  • A low-swing differential near-ground signaling (NGS) transceiver for low-power high-speed mobile I/O interface is presented. The proposed transmitter adopts an on-chip regulated programmable-swing voltage-mode driver and a pre-driver with asymmetric rising/falling time. The proposed receiver utilizes a new multiple gain-path differential amplifier with feed-forward capacitors that boost high-frequency gain. Also, the receiver incorporates a new adaptive bias generator to compensate the input common-mode variation due to the variable output swing of the transmitter and to minimize the current mismatch of the receiver's input stage amplifier. The use of the new simple and effective impedance matching techniques applied in the transmitter and receiver results in good signal integrity and high power efficiency. The proposed transceiver designed in a 65-nm CMOS technology achieves a data rate of 13 Gbps/channel and 0.3 pJ/bit (= 0.3 mW/Gbps) high power efficiency over a 10 cm FR4 printed circuit board.

Bi-directional DC-DC Converter Design and Control for step-up/step-down (승강압용 양방향 DC-DC컨버터 설계 및 제어)

  • Won, Chung-Yuen;Jang, Su-Jin;Lee, Tae-Won;Lee, Byoung-Kuk;Kim, Soo-Suck
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.20 no.5
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    • pp.49-56
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    • 2006
  • The bi-directional converter interfaces the low voltage battery to the inverter do link of FC generation system. When power flows from the low voltage side(battery: 48[V]) to the high voltage side(dc link: 380[V]), the circuit works in discharge mode (boost) to power the high voltage side load; otherwise, it works in charge mode (buck) to charge the low voltage side battery. In this paper, the 1.5[kW] active clamp current-fed full bridge converter employing MOSFETs is operated to discharge the battery whereas a voltage-fed half bridge converter employing IGBTs is operated to charge the battery.

Low Power 4-Gb/s Receiver for GND-referenced Differential Signaling (접지기반 차동신호 전송을 위한 저전력 4-Gb/s 수신단 설계)

  • Lee, Mira;Kim, Seok;Jeong, Youngkyun;Bae, Jun-Han;Kwon, Kee-Won;Chun, Jung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.9
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    • pp.244-250
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    • 2012
  • This paper describes a 4-Gb/s receiver circuit for a low-swing ground-referenced differential signaling system. The receiver employs a common-gate level-shifter and a continuous linear equalizer which compensates inter-symbol-interference (ISI) and improves voltage and timing margins. A bias circuit maintains the bias current of the level-shifter when the common level of the input signal changes. The receiver is implemented with a low-power 65-nm CMOS technology. When 4-Gb/s 400mVp-p signals are transmitted to the receiver through the channel with the attenuation of -19.7dB, the timing margin based on bit error rate (BER) of $10^{-11}$ is 0.48UI and the power consumption is as low as 0.30mW/Gb/s.

A Low-Power Design and Implementation of the Portable Device for Measuring Temperature and Humidity Based On Power Consumption Modeling (소비 전력 모델링에 입각한 휴대용 온습도 측정기의 저전력 설계 및 구현)

  • Lee, Chul-Ho;Hong, Youn-Sik
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.15 no.2
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    • pp.1027-1035
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    • 2014
  • The most important design factor for portable devices is power consumption. In this paper, in the early design stage of a mobile device which measures temperature and humidity a power consumption model will be proposed and then the overall power consumption will be estimated based on this model. We will verify previously the correctness of such estimated power consumption before implementation of the real device. That is our proposed design methodology based on power consumption model. An improved design method for efficiently reducing the current consumption in the idle mode is also presented. By implementing a real prototype of the mobile device for measuring temperature and humidity, the correctness of our proposed design methodology based on power consumption modeling will be verified.