• The Journal of the Korea institute of electronic communication sciences
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• v.2 no.3
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• pp.163-167
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• 2007

In this paper, to design 8 bit RISC Microprocessor, a method of Clock Gating to reduce electric power consumption is proposed. In order to examine the priority, the comparison results of between a 8 bit Microprocessor which is not considered Low Power consumption and which is considered Low Power consumption using a methods of Clock Gating are represented. Within the a few periods, the results of comparing with a Microprocessor not considered the utilization of Clock Gating shows that the reduction of dynamic dissipation is minimized up to 21.56%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.95-100
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• 2007

A low power PRAM using a power-dependant data inversion (PDI) scheme is proposed. The PRAM consumes large write power because large write currents are required during long time. Also, the power consumptions for storing #1# and #0# are different. The PDI circuit compares the power consumptions to store the original data and its inverted data, and then it stores the less power consuming data. Although the PDI scheme needs an additional inversion bit per data, the maximum and average powers of the PDI can be under 50% and 37.5% of the conventional write scheme, respectively. The average power for storing 8bit data is under 41%, due to the inversion bit. The 1K-bit PRAM chip with 128$\times$8bits was implemented with a 0.8${\mu}m$ CMOS technology with a 0.5${\mu}m$ GST cell.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.368-369
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• 2015

다양한 임베디드 플랫폼 및 모듈이 개발됨에 따라 최근 많은 IoT 어플리케이션은 Raspberry PI 또는 Arduino등의 메인 플렛폼을 기반으로 무선 모뎀을 UART등으로 연결하여 활용하고 있다. 본 논문에서는 이러한 범용 플렛폼에서 활용되는 RF 모듈에서의 저전력 전원관리 기법을 제안하고 실험을 통해 제안 기법의 성능의 우수성을 입증한다.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.67-72
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• 2013

A low-power bypassing Booth multiplier for mobile multimedia applications is proposed. The bypassing structure directly transfers input values to outputs without switching the internal nodes of a multiplier, enabling low-power design. The proposed Booth multiplier adopts the bypassing structure while the bypassing is usually adopted in the Braun multipliers. Simulation results show the proposed Booth multiplier achieves an 11% reduction in terms of the proposed FoM compared to prior works.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.3
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• pp.120-132
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• 2008

Networks-on-Chip (NoC) is emerging as a practical development platform for future systems-on-chip products. We propose an energy-efficient static algorithm which optimizes the energy consumption of task communications in NoCs with voltage scalable links. In order to find optimal link speeds, the proposed algorithm (based on a genetic formulation) globally explores the design space of NoC-based systems, including network topology, task assignment, tile mapping, routing path allocation, task scheduling and link speed assignment. Experimental results show that the proposed design technique can reduce energy consumption by 28% on average compared with existing techniques.

• The KIPS Transactions:PartA
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• v.18A no.3
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• pp.93-98
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• 2011

While the use of battery-powered embedded systems has been rapidly increasing, the current level of battery technology has not kept up with the drastic increase in power consumption by the system. In order to prolong system usage time, the battery size needs to be increased. The amounts of power consumption by embedded systems are determined by their hardware configuration and software for manipulating hardware resources. In spite of that, the hardware provides features for lowering power consumption, if those cannot be utilized efficiently by software including operating system, reduction in power consumption is not optimized. In this paper, we propose a BET(Break Even Time)-based scheduling method using task partition to reduce power consumption of multimedia applications in a mobile embedded system environment.

• Journal of Navigation and Port Research
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• v.36 no.3
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• pp.169-173
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• 2012

In this paper, we propose an equalizer to minimize the inter-symbol interference when PSSK(Phase Silence Shift Keying) technique is applied to the low power underwater acoustic communication. PSSK is a QPSK(Quadrature Phase Shift Keying) modulation combined with PPM(Pulse Position Modulation), and it was proposed for low power communication. However, it has poor performance due to delay spread of underwater channel. In this paper, we propose a decision feedback equalizer to minimize the error in PSSK receiver. The sea trial was performed to evaluate the performance of the proposed method. In the result, the BER of PSSK was $4.36{\times}10^{-2}$ before the equalizer was applied, but the BER of PSSK was $3.95{\times}10^{-4}$ after the proposed equalizer was applied.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.133-135
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• 2002

무선 통신의 발전으로 사용자가 휴대용 장치를 사용하여, 그들의 물리적인 위치에 상관없이 통신을 할 수 있는 이동 컴퓨팅이라는 새로운 패러다임이 생겨났다. 이러한 이등 컴퓨팅은 비연결성, 낮은 대역, 높은 대역의 가변성, 이질망의 연결, 보안성, 저 전력, 적은 저장 공간 등의 제약성을 가지고 있다. 본 논문에서는 이러한 제약 중 하나인 저 전력성을 극복하기 위하여 두 노드간의 거리에 따른 전력을 다르게 하는 방식인 전력 조절 기범(Power Adaption Scheme)에 기법에 실시간성을 고려하였다. 기존의 방식에서 전력 소비를 줄이기 위해 중간에 거쳐야 할 노드의 수가 증가하는 만큼 전송 시간이 늘어나기 때문에 시간 제약을 갖는 응용에 적절하지 못하다. 본 논문에서는 실시간성을 갖는 데이터 전송에서 소비전력을 최소화하는 라우팅 기법을 제시하였고 성능을 비교하였다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.2
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• pp.1-6
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• 2017

Due to the recent advances in IoT technologies, reducing power consumption in battery-based IoT devices becomes an important issue. An IoT device is a kind of real-time systems, and processor voltage scaling is known to be effective in reducing power consumption. However, recent research has shown that power consumption in memory increases dramatically in such systems. This paper aims at combining processor voltage scaling and low-power NVRAM technologies to reduce power consumption further. Our main idea is that if a task is schedulable in a lower voltage mode of a processor, we can expect that the task will still be schedulable even on slow NVRAM memory. We incorporate the NVRAM memory allocation problem into processor voltage scaling, and evaluate the effectiveness of the combined approach.

• The Journal of the Korea Contents Association
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• v.10 no.12
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• pp.10-17
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• 2010

In this paper, we design digital D-PHY link chip controling DSI (Display Serial Interface) that meets MIPI (Mobile Industry Processor Interface) standard. The D-PHY supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions. For low power consumption, the unit blocks in digital D-PHY are optionally switched using the clock gating technique. The proposed low power digital D-PHY is simulated and compared with conven tional one about power consumption on each transaction mode. As a result, power consumptions of TX, RX, and total in HS mode decrease 74%, 31%, and 50%, respectively. In LP mode, power reduction rates of TX, RX, and total are 79%, 40%, and 51.5%, separately. We implemented the low power MIPI D-PHY digital chip using $0.13-{\mu}m$ CMOS process under 1.2V supply.