• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.200-203
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• 2007

Devices of junction barrier schottky(JBS) structure using 4H-SiC substrates with wide energy band gaps was designed and fabricated. As a measurement results, the device of reverse I-V characteristics was shown as more than 1000 V, its design optimum length of p-grid was $3{\mu}m$ space. In this paper, I-V characteristics was modeled by using of device fabricated process conditions parameters and it was extracted that the I-V property parameters, and it was compared and analyzed with between device parameters and model parameters.

• Journal of Advanced Marine Engineering and Technology
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• v.28 no.5
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• pp.801-810
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• 2004

The Primal-Dual Interior-Point (PDIP) method is currently one of the fastest emerging topics in optimization. This method has become an effective solution algorithm for large scale nonlinear optimization problems. such as the electric Optimal Power Flow (OPF) and natural gas and electricity OPF. This study describes major theoretical developments of the PDIP method as well as practical issues related to implementation of the method. A simple quadratic problem with linear equality and inequality constraints

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.05a
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• pp.405-408
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• 1998

In this paper, We analyzed the current-voltage characteristics with n-type silicon substrates concentration and temperature variations (Room temperature, 5$0^{\circ}C$, 75$^{\circ}C$) in platinum silicide and silicon junction. Measurement electrical parameters are forward turn-on voltage, reverse breakdown voltage, barrier height, saturation current, ideality factor, dynamic resistance acceding to junction concentration of substrates and temperature variations. As a result, the forward turn-on voltage, reverse breakdown voltage, barrier height and dynamic resistance were decreased but saturation current and ideality factor were increased by substrates concentration variations. Reverse breakdown voltage and dynamic resistance were increased by temperature variations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.8
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• pp.1465-1470
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• 2017

In conventional MOSFETs, the silicon thickness is always larger than inversion layer, so that the drain induced barrier lowering (DIBL) is expressed as a function of oxide thickness and channel length regardless of silicon thickness. However, since the silicon thickness is fully depleted in the sub-10 nm low doped double gate (DG) MOSFET, the conventional SPICE model for DIBL is no longer available. Therefore, we propose a novel DIBL SPICE model for DGMOSFETs. In order to analyze this, a thermionic emission and the tunneling current was obtained by the potential and WKB approximation. As a result, it was found that the DIBL was proportional to the sum of the top and bottom oxide thicknesses and the square of the silicon thickness, and inversely proportional to the third power of the channel length. Particularly, static feedback coefficient of SPICE parameter can be used between 1 and 2 as a reasonable parameter.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.863-865
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• 2015

본 연구에서는 비대칭 이중게이트 MOSFET의 채널 내 도핑농도분포에 대한 드레인유도장벽감소(Drain Induced Barrier Lowering; DIBL)에 대하여 분석하고자한다. DIBL은 드레인 전압에 의하여 소스 측 전위장벽이 낮아지는 효과로서 중요한 단채널 효과이다. 이를 분석하기 위하여 포아송방정식을 이용하여 해석학적 전위분포를 구하였으며 전위분포에 영향을 미치는 채널도핑농도의 분포함수변화에 대하여 DIBL을 관찰하였다. 채널길이, 채널두께, 상하단 게이트 산화막 두께, 하단 게이트 전압 등을 파라미터로 하여 DIBL을 관찰하였다. 결과적으로 DIBL은 채널도핑농도분포함수의 변수인 이온주입범위 및 분포편차에 변화를 나타냈다. 특히 두 변수에 대한 DIBL의 변화는 최대채널도핑농도가 $10^{18}/cm^3$ 정도로 고도핑 되었을 경우 더욱 현저히 나타나고 있었다. 채널길이가 감소할수록 그리고 채널두께가 증가할수록 DIBL은 증가하였으며 하단 게이트 전압과 상하단 게이트 산화막 두께가 증가할수록 DIBL은 증가하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06a
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• pp.79-81
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• 2006

커널(Kernel)을 이용한 분류 방법은 넓은 마진(large margin) 분류기로서 SVM(Support Vector Machine)을 주로 사용하게 된다 하지만, 이 방법은 라그랑제 파라미터(Lagrange Parameter)의 최적화 과정을 포함함으로써 학습 과정을 쉽지 않게 만든다. 이 최적화 과정은 특히 DNA computing과 같은 단순한 과정의 설계를 통해 결과를 얻어야 하는 새로운 계산 모델에 커널을 적용하고자 했을 경우 큰 장벽이 된다. 본 논문에서는 넓은 마진을 목표로 하는 최적화 과정이 아닌 다른 라벨(label)의 데이터간의 경계 파악을 위한 간단한 커널 갱신 방법의 도입을 통해 분류기를 설계한다. 이 방법을 가우시안 커널에 적용시켜 본 결과, 반복을 통해 데이터의 구조를 찾아갈 수 있는 특성을 보여주며, 결국 넓은 마진의 최적화된 파라미터를 찾게 됨을 보여준다. 본 논문에서는 이 최적화 방법을 DNA 분자를 이용한 커널 생성 모델인 DNA 커널에 적용시켰을 때 잘 알려진 AML/ALL 데이터를 잘 분류해 냄을 보여준다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.683-685
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• 2012

This paper have presented the analysis of the change for threshold voltage and drain induced barrier lowering among short channel effects occurred in subthreshold region for double gate(DG) MOSFET with two gates to be next-generation devices, based on scaling theory. To obtain the analytical solution of Poisson's equation, Gaussian function been used as carrier distribution to analyze closely for experimental results, and the threshold characteristics have been analyzed for device parameters such as channel thickness and doping concentration and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold chatacteristics. As a result to apply scaling theory, we know the threshold voltage and drain induced barrier lowering is changed, and the deviation rate is changed for device parameters for DGMOSFET.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.145-150
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• 2013

This paper has presented the analysis for threshold voltage and drain induced barrier lowering among short channel effects occurred in subthreshold region for double gate(DG) MOSFET as next-generation devices, based on scaling theory. To obtain the analytical solution of Poisson's equation, Gaussian function has been used as carrier distribution to analyze closely for experimental results, and the threshold characteristics have been analyzed for device parameters such as channel thickness and doping concentration and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold characteristics. As a result to apply scaling theory, we know the threshold voltage and drain induced barrier lowering are changed, and the deviation rate is changed for device parameters for DGMOSFET.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.3
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• pp.579-584
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• 2012

In this paper, drain induced barrier lowering(DIBL) has been analyzed as one of short channel effects occurred in double gate(DG) MOSFET. The DIBL is very important short channel effects as phenomenon that barrier height becomes lower since drain voltage influences on potential barrier of source in short channel. The analytical potential distribution of Poisson equation, validated in previous papers, has been used to analyze DIBL. Since Gaussian function been used as carrier distribution for solving Poisson's equation to obtain analytical solution of potential distribution, we expect our results using this model agree with experimental results. The change of DIBL has been investigated for device parameters such as channel thickness, oxide thickness and channel doping concentration.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.888-891
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• 2011

In this paper, drain induced barrier lowering(DIBL) has been analyzed as one of short channel effects occurred in double gate(DG) MOSFET. The DIBL is very important short channel effects as phenomenon that barrier height becomes lower since drain voltage influences on potential barrier of source in short channel. The analytical potential distribution of Poisson equation, validated in previous papers, has been used to analyze DIBL. Since Gaussian function been used as carrier distribution for solving Poisson's equation to obtain analytical solution of potential distribution, we expect our results using this model agree with experimental results. The change of DIBL has been investigated for device parameters such as channel thickness, oxide thickness and channel doping intensity.