• The KIPS Transactions:PartA
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• v.18A no.6
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• pp.265-270
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• 2011

Even though 32-bit ISA based microprocessors are widely used more and more, 16-bit ISA based processors are still being frequently employed for embedded systems. Intel 8086, 80286, Motorola 68000, and ADChips AE32000 are the representatives of the 16-bit ISA based processors. However, due to less expressiveness of the 16-bit ISA from its narrow bit width, we need to execute more 16-bit instructions for the same implementation compared to 32-bit instructions. Because the number of executed instructions is a very important factor in performance, we have to resolve the problem by improving the expressiveness of the 16-bit ISA. In this paper, we propose a new pair register allocation algorithm to enhance an original graph-coloring based register allocation algorithm. Also, we explain about both the performance result and further research directions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.45-53
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• 2006

In this paper, we proposed a parallel hardware architecture for deblocking filter in K264/AVC. The deblocking filter has high efficiency in H.264/AVC, but it also has high computational complexity. For real time video processing, we chose a two 1-D parallel filter architecture, and tried to reduce memory access using dual-port SRAM. The proposed architecture has been described in Verilog-HDL and synthesized on Hynix 0.25um CMOS Cell Library using Synopsys Design Compiler. The hardware size was about 27.3K logic gates (without On-chip Memory) and the maximum operating frequency was 100Mhz. It consumes 258 clocks to process one macroblock, witch means it can process 47.8 HD1080P(1920pixel* 1080pixel) frames per second. It seems that it can be used for real time H.264/AVC encoding and decoding of various multimedia applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.71-78
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• 2008

In this paper, we implement the H.264/AVC baseline decoder by hardware-software partitioning under the embedded Linux Kernel 2.4.26 and the FPGA-based target board with ARM926EJ-S core. We design several IPs for the time-demanding blocks, such as motion compensation, deblocking filter, and YUV-to-RGB and they are communicated with the host through the AMBA bus protocol. We also try to minimize the number of memory accesses between IPs and the reference software (JM 11.0) which is ported in the embedded Linux. The proposed IPs and the system have been designed and verified in several stages. The proposed system decodes the QCIF sample video at 2 frame per second when 24MHz of system clock is running and we expect the bitter performance if the proposed system is designed with ASIC.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.108-116
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• 2004

In this paper, the measurement system of speed and distance of vehicles using laser is implemented and verified through the outdoor test. The implemented system consists of a laser module and a control/speed-computation module. The Former is composed of a optics part, a transmit/receive part, and a LDC(Laser Detection and Counter), and the latter is a control part that controls the laser module and a speed computation part that calculates velocity of vehicles using a microcontroller. The algorithm to compute speed has been developed to consider characteristics of laser and surrounding conditions. The implemented system has been tested and verified on the high way, and the result shows stability of the system and accuracy of the algorithm.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.128-135
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• 2004

This paper proposes a phase measurement algorithm which is based on the recursive implementation of sliding-DFT. The algorithm is designed to have a robust behavior against the erroneous factors of frequency drift, additive noise, and twiddle factor approximation. The size of phase error caused by the finite wordlength implementation of DFT twiddle factors is shown significantly lower than that of magnitude error. The drastic reduction of the phase error is achieved by the exploitation of the quadruplet symmetry characteristics of the approximated twiddle factors in the complex plane. Four channel power-line phase measurement system is also designed and implemented based on the time-multiplexed sharing architecture of the proposed algorithm. The operation of the developed system is also verified by the experiment performed under the test environment implemented with the multi-channel function generator and the on-line interfaced host processor system. The proposed algorithm's features of phase measurement accuracy and its robustness against the finite wordlength effects can provide a significant impact especially for the ASIC or microprocessor based embedded system applications where the enhanced processing speed and implementation simplicity are crucial design considerations.

• Journal of IKEEE
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• v.20 no.4
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• pp.398-411
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• 2016

SVM, a machine learning method, is widely used in image processing for it's excellent generalization performance. However, to add other data to the pre-trained data of the system, we need to train the entire system again. This procedure takes a lot of time, especially in embedded environment, and results in low performance of SVM. In this paper, we implemented an SVM trainer and classifier in an FPGA to solve this problem. We parlallelized the repeated operations inside SVM and modified the exponential operations of the kernel function to perform fixed point modelling. We implemented the proposed hardware on Xilinx ZC 706 evaluation board and used TSR algorithm to verify the FPGA result. It takes about 5 seconds for the proposed hardware to train 2,000 data samples and 16.54ms for classification for $1360{\times}800$ resolution in 100MHz frequency, respectively.

• Journal of the Korean Institute of Intelligent Systems
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• v.15 no.6
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• pp.695-700
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• 2005

In the sensor network, a lot of sensor nodes are scattered sparsely and organizes a united communication network between each node. After that, environmental information around each sensor node are gathered and analyzed. Because each node operates under resource constraint, the efficiency and hardware specification of a node should be maximized. There exist technical constraints until now but recent technical progress in IC fabrication and wireless network enables to construct a tiny embedded system, which has the properties of low cost, low power consumption, multi functions. Wireless sensor network becomes a modern research field with technical improvements, is studied in numerous laboratories, and is called as diverse different project names - Wireless Integrated Network Sensors (WINS), Mobile Ad hoc NETwork (MANET), Ubiquitous Sensor Network (USN). TinyOS is one of leading project and is widely used. In this paper, we suggest a sensor network, which uses TinyOS platforms and aims for context awareness in a home environment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.1
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• pp.199-204
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• 2017

Recently, the reagent in the laboratory can not only confirm the internal environment through the sensor but also check the status inside the reagent cabinet in real time. Also, if an abnormality occurs in the inside of the reagent cabinet, a serious accident may occur. To solve these problems, this paper proposes a reagent monitoring system that integrates reagent and ICT. The sensor data measured in real time is displayed to the user in real time through the monitor and stored in the database. In addition, by using the stored data, it is possible to inform the registered administrator in real time of the dangerous situation by informing the dangerous situation in case of danger, and to be able to check and control remotely. This can improve safety by making control and confirmation of the state of the inside of the reagent everywhere.

• Journal of Digital Contents Society
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• v.7 no.2
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• pp.103-108
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• 2006

Short-range wireless communication and networking technologies are becoming increasingly important in enabling useful mobile applications. for example, ZigBee technology is expected to provide low cost and low power connectivity for equipment that needs battery life as long as several months to several years. In addition, ZigBee can be implemented in mesh networks larger than is possible with Bluetooth. The main features of this ZigBee standard are network flexibility, low cost, very low power consumption, and low data rate in an adhoc self-organizing network among fixed, portable and moving devices. Home network/Home automation is one of the key market areas for Zigbee, with an example of a simple network This paper investigates the effect of short range wireless channel on the performance of Zigbee system and DSSS-BPSK signal transmission in AWGN, interference and Rician fading environments. And we investigate performance degradation due to interference and fading effects in short range wireless channel. In particular, the impacts of the fading and interference level on the bit error probability is shown in BER performance figures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.22-28
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• 2009

As multiprocessors have been widely adopted in embedded systems, task computation energy consumption should be minimized with several low power techniques supported by the multiprocessors. This paper proposes an energy-aware task scheduling algorithm that adopts both dynamic voltage scaling and power shutdown in multiprocessor environments. Considering the timing and energy overhead of power shutdown, the proposed algorithm performs an iterative task assignment and task ordering for multiprocessor systems. In this case, the iterative priority-based task scheduling is adopted to obtain the best solution with the minimized total energy consumption. Total energy consumption is calculated by considering a linear programming model and threshold time of power shutdown. By analyzing experimental results for standard task graphs based on real applications, the resource and timing limitations were analyzed to maximize energy savings. Considering the experimental results, the proposed energy-aware task scheduling provided meaningful performance enhancements over the existing priority-based task scheduling approaches.