• Title/Summary/Keyword: 임계경로

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East Kalman/LMS Hybrid Equalizer with Low Complexity for HDTV Channel (적은 계산량을 갖는 고속 Kalman/LMS 복합 구조 채널 등화기)

  • 서원길;박재홍;김민호;정정화
    • Proceedings of the IEEK Conference
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    • 2003.07e
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    • pp.2176-2179
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    • 2003
  • 본 논문에서는 적은 계산량을 갖는 Fast Kalman/LMS 복합 구조 등화기를 제안한다. HDTV (High Definition Television)의 채널은 긴 지연을 가지는 다중경로가 존재하기 때문에 등화기에 많은 수의 탭이 필요하다. 그러나 실제로 다중경로에 영향을 받는 심볼은 몇 개의 탭에 의해서만 발생한다 본 논문에서는 훈련기간 초기에 Fast Kalman 알고리즘을 이용하여 MSE(Mean Squared Error) 값이 특정 임계치 이하가 될 때까지 빠르게 수렴을 시키고, 심볼들에 영향을 주지 않는 탭을 제외한 나머지 탭만을 LMS (Least Mean Squre) 알고리즘으로 갱신시킴으로써 계산량을 줄이는 새로운 방법을 제안한다. 시뮬레이션 결과 제안한 방법이 기존의 Fast Kalman/LMS 복합 구조에 비해 적은 계산량으로 비슷한 수렴 속도와 MSE를 갖는 것을 보여준다.

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Dynamic Routing Algorithm based on Minimum Path-Cost in Optical Burst Switching Networks (광 버스트 스위칭 망에서 최소 경로비용 기반의 동적 경로배정 기법)

  • Lee Hae joung;Song Kyu yeop;Yoo Kyoung min;Yoo Wan;Kim Young chon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.3B
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    • pp.72-84
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    • 2005
  • Optical burst switching networks usually employ one-way reservation by sending a burst control packet with a specific offset time, before transmitting each data burst Same. Due to such a Property, burst-contentions occur when multiple bursts contend for the same wavelength in the same output link simultaneously in a node, leading to burst losses, eventually degrading the quality of service. Therefore, in this paper, we propose a dynamic routing algorithm using minimum local state information in order to decrease burst-contentions. In this proposed scheme, if burst loss rate exceeds a threshold value at a certain node, a new alternative routing path is chosen according to burst priority and location of burst generation, which enables the contending bursts to detour around the congested link. Moreover, for reducing the effect of sending bursts on the primary path due to the alternative path, we also apply a minimum path-cost based routing on link-cost concept. Our simulation results show that proposed scheme improves the network performance in terms of burst loss probability and throughput by comparing with conventional one.

A study on prediction of heavy rainfall due to cloud cluster associated with meso-low (중규모 저기압과 연관된 구름무리에 의한 호우의 예측에 관한 연구)

  • Lee, Yun Kyu;Lee, Tae-Young
    • Proceedings of the Korea Water Resources Association Conference
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    • 2017.05a
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    • pp.331-331
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    • 2017
  • 2011 년부터 2014 년까지 4 년간의 여름철에 한반도에 비교적 많은 강수를 남긴 23 개의 중규모 저기압-구름무리 집중호우 사례를 선정하여, 이들 사례에서의 중규모 저기압 발생과 이동 그리고 그것에 동반된 강수계에 의한 강수 발생을 수치예측하는 실험을 수행하였다. WRF 모델을 이용하여 12 km와 4 km 수평격자 크기로 수치실험을 진행하였으며, 각 사례에 대해 중규모 저기압이 발생한 시점을 초기 시각으로 하여 수치적분을 수행하였다. 수치실험 결과와 AWS 강수량 관측 자료를 $0.1^{\circ}{\times}0.1^{\circ}$ 격자에 각각 내삽한 후 비교하였다. 12 km 격자 실험에서는 25 mm/12h 문턱값에 대해 23개의 사례 중 9개 (39 %)만이 0.3이 넘는 성공임계지수(TS)를 나타냈고, 50 mm/12h 문턱값에 대해서는 17개 사례 중 7개 (41 %)의 사례에서 0.3이 넘는 TS가 나타났다. 4 km 실험에서는 25 mm/12h 문턱값에 대해 23개의 사례 중 10개 (43 %) 사례에서 0.3이 넘는 TS 값이 나타났고, 50 mm/12h 문턱값에 대해서는 17개 사례 중 7개 (41 %)로 나타나 WRF 모델의 수평격자 크기와 관계없이 비슷한 성능을 보였다. 중규모 저기압이 진행하는 경로에 따라 예측 능력에 차이가 나타났다. 23개 사례를 중규모 저기압 발생지점으로부터의 이동경로에 따라 준 직선 경로 사례 그룹, 곡선형 경로 사례 그룹, 정체사례 그룹으로 분류하여 각 그룹에 대해 예측 능력을 조사한 결과, 직전 경로 사례들에 대한 4km 격자 모델 예측은 55 %의 사례에서 0.3보다 큰 TS값을 보여, 30 %의 사례에서 0.3 이상의 TS 값을 보인 곡선형 경로 사례들에 대한 예측보다 상대적으로 높은 예측 신뢰도를 보여 주었다.

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Performance Evaluation of control and management protocol for Dynamic lightpath setup based GMPLS network (GMPLS 기반의 동적 경로 설정을 위한 제어 및 관리 프로토콜 성능 평가)

  • Kim Kyoung-Mok;Oh Young-Hwan
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.12
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    • pp.9-14
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    • 2004
  • As the internet traffic type and size have bun diversified in recent years, the GMPLS-based distributed control and management protocol have surfaced as a serious issue for dynamic optical lightpath setup. In this reason, we investigated and analyzed network performance and protocols using global information-based link state approach and local information based link state approach. We calculated connection setup time, required control bandwidth and setup blocking probability that made from network update period and threshold metrics according to traffic arrival rate. The evaluated results will be used in broadband network and adopted for high speed network in the future widely.

Switch Architecture and Routing Optimization Strategy Using Optical Interconnects for Network-on-Chip (광학적 상호연결을 이용한 네트워크-온-칩에서의 스위치 구조와 라우팅 최적화 방법)

  • Kwon, Soon-Tae;Cho, Jun-Dong;Han, Tae-Hee
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.9
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    • pp.25-32
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    • 2009
  • Recently, research for Network-on-chip(NoC) is progressing. However, due to the increase of system complexity and demand on high performance, conventional copper-based electrical interconnect would be faced with the design limitation of performance, power, and bandwidth. As an alternative to these problems, combined use of Electrical Interconnects(EIs) and Optical Interconnects(OIs) has been introduced. In this paper we propose efficient routing optimization strategy and hybrid switch architecture, which use OIs for critical path and EIs for non-critical path. The proposed method shows up to 25% performance improvement and 38% power reduction.

A Pattern Comparison Algorithm for Pruning Fault Candidates (고장 대상 후보를 줄이기 위한 패턴 비교 알고리즘)

  • Cho, Hyung-Jun;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.11
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    • pp.82-88
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    • 2007
  • In this paper, we present a pattern comparison algorithm for reducing fault candidate lists. The number of fault candidates determines the total fault simulation time. To decrease the total fault diagnosis time, the reduction of the number of fault candidates is essential. Critical path tracing determines fault candidate lists detected by a set of tests using a backtracing algorithm starting at the primary outputs of a circuit. The proposed algorithm reduces fault candidates comparing failing patterns with good patterns during critical path tracing process. As we reduce all fault candidates of the circuit to more accurately suspected fault candidates, we can greatly reduce fault simulation time. The proposed algorithm greatly increases simulation speed than that of a conventional backtracing method. The proposed algorithm is applicable to both combinational and sequential circuits. Experimental results on ISCAS#85 and ISCAS#89 benchmark circuits showed fault candidates are pruned and fault diagnosis time is also decreased in proportion to fault candidate decrease.

Effect of Micro-Cracks on Chloride Ions Penetration of Concrete II: Examination of Critical Crack Width (미세균열이 콘크리트의 염소이온 침투에 미치는영향 II: 임계 균열폭의 고찰)

  • Yoon, In-Seok
    • Journal of the Korea Concrete Institute
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    • v.19 no.6
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    • pp.707-715
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    • 2007
  • The vulnerability of concrete to its environment is significantly dependent on the fact that concrete is a porous material. For well-consolidated and well-cured concrete, its service life is a very long and an entrance of aggressive substance might be only pores. However, for cracked concrete, cracks should be preferential channel for the penetration of aggressive substance such as chloride ions. The effect of crack on chloride penetration depends on its size for example, crack width and crack depth. The purpose of this study is examining the effect of crack width and crack depth on chloride penetration. In order to visualize chloride penetration via cracks, RCM (rapid chloride migration) testing is accomplished. Crack width is examined using an optical microscope and CMOD value is used to estimate average crack width. From the examination on the trend of chloride diffusion coefficients of concrete specimens with various crack widths, a critical crack width and a critical crack depth are found out.

Single chip multi-function peripheral image processor with unified binarization architecture (통합된 이진화 구조를 가진 복합기용 1-Chip 영상처리 프로세서의 개발)

  • Park, Chang-Dae;Lee, Eul-Hwan;Kim, Jae-Ho
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.36S no.11
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    • pp.34-43
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    • 1999
  • A high-speed image processor (HIP) is implemented for a high-speed multi-function peripheral. HIP has a binarization architecture with unified data path. It has the pixel-by-pixel pipelined processing to minimize size of the external memory. It performs pre-processing such as shading correction, automatic gain control (AGC), and gamma correction, and also drives external CCD or CIS modules. The pre-processed data can be enlarged or reduced. Various binarizatin algorithms can be processed in the unified archiecture. The embedded binarization algorithms are simple thresholding, high pass filtering, dithering, error diffusion, and thershold modulated error diffusion. These binarization algorithms are unified based on th threshold modulated error diffusion. The data path is designed to share the common functional block of the binarization algorithms. The complexity of the controls and the gate counts is greatly reduced with this novel architecture.

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The Dosimetric Effect on Real PTV and OARs at Various Image Fusion Protocol for Pituitary Adenomas (뇌하수체 종양의 방사선 수술 시 영상 융합 프로토콜이 실제 PTV와 OAR 선량에 미치는 영향)

  • Lee, Kyung-Nam;Lee, Dong-Joon;Suh, Tae-Suk
    • Progress in Medical Physics
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    • v.21 no.4
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    • pp.354-359
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    • 2010
  • The purpose of this study is to verify the dosimetric effect on real PTV (planning target volume) coverage and safety of OARs (organs at risk) at various image fusion protocol-based radiosurgery plan for pituitary adenomas. Real PTV coverage and its variation was acquired and maximum dose and the volume absorbing above threshold dose were also measured for verifying the safety of optic pathway and brainstem. The protocol that can reduce superior-inferior uncertainty by using both axial and coronal MR (magnetic resonance) image sets shows relatively lower values than that of case using only axial image sets. As a result, the image fusion protocol with both axial and coronal image sets can be beneficial to generate OAR-weighted radiosurgery plan.

Design of Decimal Floating-Point Adder for High Speed Operation with Leading Zero Anticipator (선행 제로 예측기를 이용한 고속 연산 십진 부동소수점 가산기 설계)

  • Yun, Hyoung-Kie;Moon, Dai-Tchul
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.2
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    • pp.407-413
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    • 2015
  • In this paper, a DFPA(decimal floating-point adder) designed a pipeline structure that uses a LZA(leading zero anticipator) to reduce critical route to shorten delay to improve the speed of operation processing. The evaluation and verification of performance of proposed DFPA applied the Flowrian tool with simulation and Cyclone III FPGA was set as the target on the Quartus II tool for the synthesis. The proposed method compared and verified to proposed the other method using same input data. As a result, the performance of proposed method is improved 11.2% and 5.9% more than L.K.Wang's method and etc.. Also, it is confirmed that improvement of operation processing speed and reduction of the number of delay elements on critical path.