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http://dx.doi.org/10.6109/jkiice.2015.19.2.407

Design of Decimal Floating-Point Adder for High Speed Operation with Leading Zero Anticipator  

Yun, Hyoung-Kie (Department of Information and Communication Engineering, Hoseo University)
Moon, Dai-Tchul (Department of Information and Communication Engineering, Hoseo University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.19, no.2, 2015 , pp. 407-413 More about this Journal
Abstract
In this paper, a DFPA(decimal floating-point adder) designed a pipeline structure that uses a LZA(leading zero anticipator) to reduce critical route to shorten delay to improve the speed of operation processing. The evaluation and verification of performance of proposed DFPA applied the Flowrian tool with simulation and Cyclone III FPGA was set as the target on the Quartus II tool for the synthesis. The proposed method compared and verified to proposed the other method using same input data. As a result, the performance of proposed method is improved 11.2% and 5.9% more than L.K.Wang's method and etc.. Also, it is confirmed that improvement of operation processing speed and reduction of the number of delay elements on critical path.
Keywords
Decimal Floating-Point Adder; Leading Zero Anticipator; Pipeline Processing Structure; High-speed Operation;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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1 IEEE, IEEE 754-2008 Standard for Floating-Point Arithmetic, 2008.
2 Lipsa Sahu, Ruby Dev, "An Efficient IEEE 754 Compliant FPU using verilog", Department of Computer Science and Engineering National Institute of Technology Rourkela, 2012.
3 M. Cowlishaw, "Decimal Floating-Point: Algorithm for Computers," IEEE Symp. on Computer Arithmetic, pp. 104-111, 2003.
4 Jong-Hyeon Kim, Parallel Computer Architecture, New ed. Saeng-Neung Publish, 2010. 10.
5 L. K. Wang, C. Tsen, M. J. Schulte, and D. Jhalani, "Benchmarks and Performance Analysis of Decimal Floating-Point Applications", Computer Design, ICCD 2007. 25th International Conference on, pp. 164-170, 2007.
6 Hyoung-Kie Yun, Dai-Tchul Moon, "Design of Parallel Decimal Floating-Point Arithmetic Unit for High-speed Operations", JKIICE Journal, No. 17(12), pp. 2921-2926, 2013. 12.   과학기술학회마을   DOI
7 Mohamed H. Amin, Ahmed M. Eltantawy, Alhassan F. Khedr, Hossam A. H. Fahmy, Ahmed A. Naguib, "Efficient Decimal Leading Zero Anticipator Designs", Signals, Systems and Computers (ASILOMAR), 2011 Conference Record of the Forty Fifth Asilomar Conference on, p. 139-143, 2011. 11.
8 Steven Carlough, Adam Collura, Silvia Mueller, Michael Kroener, "The IBM zEnterprise-196 Decimal Floating- Point Accelerator", Computer Arithmetic (ARITH), 2011 20th IEEE Symposium on, PP. 139 - 146, 2011.