• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1528-1535
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• 1994

In this paper, a filtered-X LMS algorithm by new error path identification method is proposed for active noise control system. The proposed algorithm identifies accurately the error path transfer function using three microphones and the control of error signal through double loop scheme with on-line. In the computer simulation using the sinusoidal and the practical duct noise, the proposed algorithm reduces noise level about 29.1dB and 10.4dB, respectively. We can observe the improvement of about 0.5dB and 2.5dB in noise level compared with that obtained using the filtered-X LMS algorithm of Eriksson model.

• Journal of the Korean Society for Precision Engineering
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• v.29 no.1
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• pp.79-86
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• 2012

This paper proposes PID and RIC (Robust Internal-loop Compensator) based motion controller using dual learning algorithm for position control of linear synchronous motor respectively. Its gains are auto-tuned by using two learning algorithms, reinforcement learning and neural network. The feedback controller gains are tuned by reinforcement learning, and then the feedforward controller gains are tuned by neural network. Experiments prove the validity of dual learning algorithm. The RIC controller has better performance than does the PID-feedforward controller in reducing tracking error and disturbance rejection. Neural network shows its ability to decrease tracking error and to reject disturbance in the stop range of the target position and home.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.914-915
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• 2008

Generally, inverter controller for UPS or renewable energy system have been used double loop PI controller, But it is hard to get controller gains for double loop controller because it is high order. Futhermore, to consider time specification is difficult too. This paper presents the way how to make double PI loop controller for inverter satisfied with time specification using CRA method and verify efficiency of it using Matlab and Psim.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.77-86
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• 2016

This paper describes a dual-mode reference-less CDR(Clock Data Recovery) operating at full / half-rate and its operation algorithm. Proposed reference-less CDR consists of a frequency detector, a phase detector, a charge pump, a loop filter, a voltage controlled oscillator, and a digital block. The frequency and phase detectors operate at both full / half-rate for dual-mode operation and especially the frequency detector is capable of detecting the difference between data rate and clock frequency in the dead zone of general frequency detectors. Dual-mode reference-less CDR with the proposed algorithm can recover the data and clock within 1.2-1.3 us and operates reliably at both full-rate (2.7 Gb/s) and half-rate (5.4 Gb/s) with 0.5-UI input jitter.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.3
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• pp.267-275
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• 2007

This paper presents about energy input and output modeling for a flywheel energy storage system that can store and supply mechanical energy, which is emerging as one of clean energy sources, and the analysis and control of a PWM inverter system. Moreover, this paper describes flywheel's characteristics related to variations of mechanical and electrical parameters like as voltage and current versus speed characteristics formed as numerical formula and thus simulate behaviour-status of flywheel energy. Also for comparison and analysis between PI control and PDFF control, the modeling, design and analysis to the single-phase full bridge inverter with double loop feedback control is accomplished through numerical description and simulation. Finally, under load condition 0.1[pu], 1[pu]. it is validated that harmonic characteristics for voltage and current wave is controlled within 5% below even dynamics condition.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.74-84
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• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.79-85
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• 2004

A digitally-controlled analog-block inevitably undergoes the bang-bang oscillations which may cause a big amplitudes of the glitches if the oscillation occurs at the MSB transition points of a binary counter. The glitch results into the jitter noise for the case of the DLL. In this paper, we devise a new counter code that has the hysteresis in the bit transitions in order to prevent the transitions of the significant counter-bits at the locking state. The maximum clock jitter is simulated to considerably reduce over the voltage-temperature range guaranteed by specifications. The counter is employed to implement the high speed packet-base DRAM and contributes to the maximized valid data-window.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.40 no.1
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• pp.1-8
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• 2016

In this study, we propose a control algorithm for Inertially Stabilized Platforms (ISP), which combines Disturbance Observer (DOB) with conventional proportional integral derivative (PID) control algorithm. A single axis ISP system was constructed using a direct drive motor. The joint friction was modeled as a nonlinear function of joint speed while the accuracy of the model was verified through experiments and simulation. In addition, various Q-filters, which have different orders and relative degrees of freedom (DOF), were implemented. The stability and performance of the ISP were compared through experimental study. The performance of the proposed PID-plus-DOB algorithm was compared with the experimental results of the conventional double loop PID control under artificial vehicle motion provided motion simulator with six DOF.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.21-26
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• 2016

This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.6
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• pp.23-36
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• 2005

PLLs have been widely used for many applications including communication systems. This paper presents a VCO with an improved negative skewed delay scheme and a PLL using this VCO. The proposed VCO and PLL are intended for replacing traditional LC oscillators and PLLs used in communication systems and other applications. The circuit designs of the VCO and PLL are based on 0.18um CMOS technology with 1.8V supply voltage. The proposed VCO employs subfeedback loops using pass-transistors and needs two opposite control voltages for the pass transistors. The subfeedback loops speed up oscillation depending on the control voltages and thus provide a high oscillation frequency. The two voltage controls have opposite frequency gain characteristics and result in low phase-noise. The 7-stage VCO in 0.18um CMOS technology operates from $3.2GHz\~6.3GHz$ with phase noise of about -128.8 dBc/Hz at 1MHz frequency onset. For 1.8V supply voltage, the current consumption is about 3.8mA. The proposed PLL has dual loop-filters for the proposed VCO. The PLL is operated at 5GHz with 1.8V supply voltage. These results indicate that the proposed VCO can be used for radio frequency operations replacing LC oscillators. The circuits have been designed and simulated using 0.18um TSMC library.