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A Radio-Frequency PLL Using a High-Speed VCO with an Improved Negative Skewed Delay Scheme  

Kim, Sung-Ha (System IC Div., LG Electronics)
Kim, Sam-Dong (Dept. of Electronics Engineering, Dongguk Univ.)
Hwang, In-Seok (Dept. of Electronics Engineering, Dongguk Univ.)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.42, no.6, 2005 , pp. 23-36 More about this Journal
Abstract
PLLs have been widely used for many applications including communication systems. This paper presents a VCO with an improved negative skewed delay scheme and a PLL using this VCO. The proposed VCO and PLL are intended for replacing traditional LC oscillators and PLLs used in communication systems and other applications. The circuit designs of the VCO and PLL are based on 0.18um CMOS technology with 1.8V supply voltage. The proposed VCO employs subfeedback loops using pass-transistors and needs two opposite control voltages for the pass transistors. The subfeedback loops speed up oscillation depending on the control voltages and thus provide a high oscillation frequency. The two voltage controls have opposite frequency gain characteristics and result in low phase-noise. The 7-stage VCO in 0.18um CMOS technology operates from $3.2GHz\~6.3GHz$ with phase noise of about -128.8 dBc/Hz at 1MHz frequency onset. For 1.8V supply voltage, the current consumption is about 3.8mA. The proposed PLL has dual loop-filters for the proposed VCO. The PLL is operated at 5GHz with 1.8V supply voltage. These results indicate that the proposed VCO can be used for radio frequency operations replacing LC oscillators. The circuits have been designed and simulated using 0.18um TSMC library.
Keywords
PLL; VCO; Dual Loop-Filter; Negative Skewed Delay Scheme; Subfeed Back Loop;
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