• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.65-73
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• 2003

This paper presents the implementation of an analog signal-processing ASIS to detect an angular velocity signal from a vibrator angular velocity detection sensor. The output of the sensor to be charge appeared as the variation of the capacitance value in the structure of the sensor was detected using charge amplifiers and a self oscillation circuit for driving the sensor was implemented with a sinusoidal self oscillation circuit using the resonance characteristics of the sensor. Specially an automatic gain control circuit was utilized to prevent the deterioration of self-oscillation characteristics due to the external elements such as the characteristic variation of the sensor process and the temperature variation. The angular velocity signal, amplitude-mod)Hated in the operation characteristics of the sensor, was demodulated using a synchronous detection circuit. A switching multiplication circuit was used in the synchronous detection circuit to prevent the magnitude variation of detected signal caused by the amplitude variation of the carrier signal. The ASIC was designed and implemented using 0.5${\mu}{\textrm}{m}$ CMOS process. The chip size was 1.2mm x 1mm. In the experiment under the supply voltage of 3V, the ASIC consumed the supply current of 3.6mA and noise spectrum density from dc to 50Hz was in the range of -95 dBrms/√Hz and -100 dBrms/√Hz when the ASIC, coupled with the sensor, was in normal operation.

• Parasites, Hosts and Diseases
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• v.35 no.4
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• pp.233-238
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• 1997

A small coastal village of Muan-gun, Chollanam-do, was surveyed for intesti- nal fluke infections, especially heterophyids such as Heterophwes nocens and Ftsiniopsis summc by fecal examination on 108 inhabitants. The egg Positive rate of heterophyids was very high. 75.0%, and that of other parasites was comparatively low.0.9-3.7% by parasite species . After treatment of 20 patients showing high E. P. G. with praziquantel and purging with Mgs04, total 3,864 specimens of H. nocens were collected from the diarrheic stools of all the patients treated (3-1,338 individuallyl and total 703 p. summc were harvested from 18 patients (1-170 individually), together loth several other species of flukes. Other flukes included Stictodora jlscotn (164 specimens from 4 patients), Heterophwopsis continuo (2 from 2 patients), and Gwmnophalloides seoi (4 from 3 patients). From this study, the sutra- veyed coastal area of Muan-gun, Chollanam-do was proven to be a new endemic focus of H. nocens and p. summa. The occurrence of a few infected cases surf:mists that this area should also be a low-grade endemic area of S. Juscctc, H. continuo, and G. seoi.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.39-47
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• 1998

A fourth-order $\Sigma$-$\Delta$ modulator is designed and implemented in 0.6 $\mu\textrm{m}$ CMOS technology. The modulator is verified by introducing nonlinear factors such as DC gain and slew rate in system model that determines the transfer function in S-domain and in time-domain. Dynamic range is more than 110 dB and the peak SM is 102.6 dB at a clock rate of 2.8224 MHz for voiceband signal. The structure of a ∑-$\Delta$ modulator is a modified fourth-order ∑-$\Delta$ modulator using direct feedback loop method, which improves performance and consumes less power. The transmission zero for noise is located in the first-second integrator loop, which reduces entire size of capacitors, reduces the active area of the chip, improves the performance, and reduces power dissipation. The system is stable because the output variation with respect to unit time is small compared with that of the third integrator. It is easy to implement because the size of the capacitor in the first integrator, and the size of the third integrator is small because we use the noise reduction technique. This paper represents a new design method by modeling that conceptually decides transfer function in S-domain and in Z-domain, determines the cutoff frequency of signal, maximizes signal power in each integrator, and decides optimal transmission-zero frequency for noise. The active area of the prototype chip is 5.25$\textrm{mm}^2$, and it dissipates 10 mW of power from a 5V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.60-68
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• 2010

In case of sensorineural hearing loss, auditory perception can be activated by electrical stimulation of the nervous system via electrode implanted into the cochlea or auditory nerve. Since the tonotopic map of the human auditory nerve has not been definitively identified, the recording of auditory nerve signal with microelectrode is desirable for determining the tonotopic map. This paper proposes the multi-channel analog front-end for auditory nerve signal detection. A channel of the proposed analog front-end consists of an AC coupling circuit, a low-power 4th-order Gm-C LPF, and a single-slope ADC. The AC coupling circuit transfers only AC signal while it blocks DC signal level. Considering the bandwidth of the auditory signal, the Gm-C LPF is designed with OTAs adopting floating-gate technique. For the channel-parallel ADC structure, the single-slope ADC is used because it occupies the small silicon area. Experimental results shows that the AC coupling circuit and LPF have the bandwidth of 100 Hz - 6.95 kHz and the ADC has the effective resolution of 7.7 bits. The power consumption per a channel is $12\;{\mu}W$, the power supply is 3.0 V, and the core area is $2.6\;mm\;{\times}\;3.7\;mm$. The proposed analog front-end was fabricated in a 1-poly 4-metal $0.35-{\mu}m$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.28-34
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• 2010

In this paper, the transceiver for RFID reader using 13.56MHz as a carrier frequency and meeting International Standard ISO 14443 type A, 14443 type B and 15693 is presented. The receiver is composed of envelope detector, VGA(Variable Gain Amplifier), filter, comparator to recovery the received signal. The proposed automatic reference voltage generator, positive peak detector, negative peak detector, and data slicer circuit can adjust the decision level of reference voltage over the received signal amplitudes. The transmitter is designed to drive high voltage and current to meet the 15693 specification. By using inductor loading circuit which can swing more than power supply and drive large current even under low impedance condition, it can control modulation rate from 30 percent to 5 percent, 100 perccnt and drive the output currents from 5 mA to 240 mA depending on standards. The 13.56 MHZ RFID reader is implemented in $0.18\;{\mu}m$ CM08 technology at 3.3V single supply. The chip area excluding pads is $1.5mm\;{\times}\;1.5mm$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.7-14
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• 2008

In this paper, we designed the HVIC(High Voltage Gate Driver IC) which has improved noise immunity characteristics and high driving capability. Operating frequency and input voltage range of the designed HVIC is up to 500kHz and 650V, respectively. Noise protection and schmitt trigger circuit is included in the high-side level shifter of designed IC which has very high dv/dt noise immunity characteristic(up to 50V/ns). And also, rower dissipation of high-side level shifter with designed short-pulse generation circuit decreased more that 40% compare with conventional circuit. In addition, designed HVIC includes protection and UVLO circuit to prevent cross-conduction of power switch and sense power supply voltage of driving section, respectively. Protection and UVLO circuit can improve the stability of the designed HVIC. Spectre and Pspice circuit simulator were used to verify the operating characteristics of the designed HVIC.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.123-130
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• 2016

High-frequency induction heating equipment can heat the metal by applying a High-Frequency power to the resonant circuit. The resonance circuit is composed of the work coil and the conduction-cooled power capacitor, it influences the performance of the heat treatment equipment according to the characteristics of the capacitor. However, dependence on conduction-cooled power capacitor's import is high due to lack of core technology research and development. Minimizing the generation of internal heat transmitted inside during LC resonance, reduce the reactive power loss, there is a need for a capacitor within the voltage characteristic outstanding. To implement localization it is vital that prior study of the analysis on the frequency response characteristic for the finished capacitor advanced manufacturer be implemented. Studying the interpolation method to read the value at any point of the characteristic curve for a given log-log scale was applied to the analysis tool of the capacitor by my proposed algorithm. The simulation for reproducing frequency response curves was attempted by assuming a capacitor in a simplified series equivalent RC circuit to obtain the equivalent series resistance value. It was confirmed that the reproduction rate was the result value above 83% as compared to the simulation of the properties and characteristics on the actual reactive power for Peak value, and that the algorithm can be applicable when analyzing and predicting the characteristic curves of a simpled model capacitor.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.352-361
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• 2010

In this paper, a compact 20 W block-up-converter for C-band satellite communication is designed and implemented. The designed block up-converter consists of an intermediate frequency circuit, a mixer and local oscillator, a driver amplifier, a solid-state power amplifier, waveguide circuits, and a power supply module. To reduce the size of the block-up-converter, all circuits are assembled within an housing, so its dimension is just $21{\times}14{\times}11cm^3$. Especially, the waveguide filter and microstirp-to-waveguide transition are easily implemented using an housing. Also, to meet spurious and harmonics specification, various compact microstrip filters including an elliptic filter are integrated. Measurement results show that the developed block up-converter has good electrical performances: the output power of 43.7 dBm, the minimum gain of 65 dB, the gain flatness of ${\pm}1.84$, the IMD3 of -35 dBc, and the harmonic level of -105 dBc.

• Journal of Gastric Cancer
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• v.7 no.2
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• pp.102-106
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• 2007

Gastric carcinoid tumor is a neoplasm that arises from enterochromaffine-like (ECL) cells in the gastric fundus. It is a rare disease that comprises less than 2% of all gastric neoplasms; however its incidence has been recently increasing. We experienced one case of gastric carcinoid tumor that was revealed to be multiple polypoid lesions. A 29-year-old female patient visited a hospital three years ago due to syncope. The blood hemoglobin was measured as 6.0 g/dl. Gastroscopy revealed multiple polypoid lesions with bleeding; therefore endoscopic clipping was performed. The polyps were diagnosed as carcinoid tumor via endoscopic biopsy. She was transferred to our hospital because of persistent iron deficiency anemia that was caused by bleeding at the gastric polyps. Gastroscopy revealed more than twenty various-sized polypoid lesions from the mid-body to the antrum. The blood hemoglobin level was 9.0g/dl. Total gastrectomy was performed under the diagnosis of gastric carcinoid tumor with bleeding. All of the gastric polyps were diagnosed as carcinoid tumors, and any metastasis to the regional lymph nodes was not found. Eighteen months after operation, the blood hemoglobin was increased to 12.8g/dl with no evidence of recurrence. Surgical resection should be considered for treating gastric carcinoid tumor with continuous bleeding.

• Journal of Navigation and Port Research
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• v.26 no.1
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• pp.22-27
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• 2002

The 25 Watt hybrid MIC SSPA has been developed in the frequency rang from 1.6265 GHz to 1.6465 GHz for uplink of INMARST's earth station. To simplify the fabrication process, the whole system is designed of two parts composed of a friving amplifier and a power amplifier. The Motorolas MRF-6401 is used for driving part, the Motorolas MRF-16006 and MRF-16030 is used the power amplifier. We reduced weight and volume of high power amplifier through arranging the bias circuits in the same housing. The realized SSPA has more than 30 dB for gain within 20 MHz bandwidth, and the voltage standing wave ratios(VSWR) of input and output port are less than 1.7, respectively. The output power of 44 dBm is achieved at the 1 dB gain compression point of 106365 GHz These results reveal a high power amplifier of 25 Watt which is the design target. The Proposed SSPA manufacture techniques in this paper can be applied to the implementation of high power amplifiers for some radars and SCPC.