• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.12
• /
• pp.2326-2332
• /
• 2016

In this paper, the proposed small size PLL works stable with the discrete loop filter which is controlled by voltage controlled oscillator's output signal. A switch controlled loop filter is introduced into the proposed PLL instead of a conventional $2^{nd}$-order loop filter. Those three switches are controlled by the very high frequency output signal of voltage controlled oscillator. The switches are also controlled by UP/DN signals and 'on/off' depending the presence of UP/DN signals. A negative feedback functioned capacitor with a switch does make it possible to integrate the PLL into a single chip. The proposed PLL works stably even though a total of small 180pF capacitor used in the discrete loop filter. The proposed PLL has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.15 no.2
• /
• pp.89-94
• /
• 2022

In this paper, a discrete-time loop filter(DLF) phase-locked loop with a Frequency Fluctuation Converting Circuit(FFCC) has been proposed. Discrete-time loop filter can improve spur characteristic by connecting the charge pump and voltage oscillator discretely unlike a conventional continuous-time loop filter. The proposed PLL is designed to operate stably by the internal negative feedback loop including the SSC acting as a negative feedback to the discrete-time loop filter of the external negative feedback loop. In addition, the phase noise is further improved by reducing the magnitude of the loop filter output voltage variation through the FFCC. Therefore, the magnitude of jitter has been reduced by 1/3 compared to the conventional structure. The proposed phase locked loop has been simulated with Hspice using the 1.8V 180nm CMOS process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.05a
• /
• pp.154-156
• /
• 2016

In this paper, the proposed small size PLL works stable with the discrete loop filter which is controlled by voltage controlled oscillator's output signal. Sampling and a small size capacitor functioned negative feedback with switch does make it possible to integrate the PLL into a single chip. The proposed PLL is designed by 1.8V 0.18um CMOS process.

• Proceedings of the KIPE Conference
• /
• 2017.07a
• /
• pp.194-195
• /
• 2017

본 논문은 독립형 마이크로그리드에서 BESS-디젤발전기 연계운전 시, 동기 인덕턴스와 LCL 필터의 상호간섭을 고려한 CVCF 제어기를 설계하고 해석하였다. CVCF 제어의 외부루프는 비례-공진(PR)을 이용한 기본파 전압제어이고, 내부루프는 제어 안정도 향상을 위한 커패시터 전류제어로 구성된 이중 루프 구조이다. 인버터 $1.5T_s$ 시지연을 고려하여 모델링을 설계하고, 이산시간 영역에서의 근궤적 기법을 통해 CVCF 제어의 안정도를 해석하였다. 50kW BESS-디젤발전기로 구성된 시뮬레이션을 통해 안정도 해석과 동일한 결과를 도출함으로써 설계된 CVCF 제어기를 검증하였다.

• Proceedings of the KIPE Conference
• /
• 2015.11a
• /
• pp.11-12
• /
• 2015

본 논문은 LCL 필터를 사용하는 계통연계형 인버터의 안정적인 전류제어를 위한 공진주파수와 샘플링주파수의 관계 분석을 통해 주파수 및 이산시간영역에서 전류제어 안정도를 해석, 시뮬레이션 및 실험을 통해 검증하였다. 능동댐핑을 포함하지 않는 계통전류 제어의 경우, 공진주파수가 샘플링주파수의 1/6이 되는 $f_{base}$보다 높은 영역에 위치하면 안정, 낮은 영역에 위치하면 불안정한 특성을 분석하였고, 공진주파수 변화에 따른 전류제어루프의 안정도 해석을 기반으로 7kW 계통연계형 인버터 Psim 시뮬레이션 및 실험을 통해 동일한 결과를 도출함으로써 주파수간의 관계 분석 및 안정도 해석의 타당성을 검증하였다.