• The Journal of Korean Institute of Information Technology
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• v.16 no.11
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• pp.77-84
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• 2018

In this paper, the circular polarization microstrip patch antenna using the T-junction power divider is proposed. The operating frequency of the proposed antenna is ISM band of 2.4GHz and the circular polarization is induced by feeding a phase difference of $90^{\circ}$ in two edges. The structure of the antenna consists of a general patch and a T-junction power divider. Furthermore, to optimize the proposed antenna, it is analyzed the reflection coefficient, the axial ration and the radiation pattern. The impedance bandwidth of the antenna is observed to be 40MHz within a range of 2.39 to 2.43GHz, similarly, the axial ratio bandwidth is observed having the bandwidth of about 12MHz in 2.398 to 2.410GHz range. The radiation pattern of the antenna is seen to be right circular polarization. Furthermore, the gain of the antenna is observed to be 2.04 and 3.4dBic at XZ and YZ-plane, respectively.

• Composites Research
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• v.34 no.1
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• pp.47-50
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• 2021

In this paper, the Curing process for Epoxy Molding Compound (EMC) Package was developed by comparing the performance of the EMC/Cu Bi-layer package manufactured by the conventional Hot Press process system and Carbon Nanotubes (CNT) Heater process system of the surface heating system. The viscosity of EMC was measured by using a rheometer for the curing cycle of the CNT Heater. In the EMC/Cu Bi-layer Package manufactured through the two process methods by mentioned above, the voids inside the EMC was analyzed using an optical microscope. In addition, the interfacial void and warpage of the EMC/Cu Bi-layer Package were analyzed through C-Scanning Acoustic Microscope and 3D-Digital Image Correlation. According to these experimental results, it was confirmed that there was neither void in the EMC interior nor difference in the warpage at room temperature, the zero-warpage temperature and the change in warpage.

• Journal of Advanced Navigation Technology
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• v.27 no.5
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• pp.540-545
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• 2023

AESA radar is able to instantaneously and adaptively position and control the beam, and this enables to have interleaved mode in modern airborne AESA radar which can maximize situational awareness capability. Interleaved mode provides two or more modes simultaneously, such as Air to Air mode and Sea Surface mode by time sharing technique. In this interleaved mode, performance degradation is inevitable, compared with single mode operation, and effective resource allocation is the key component for the success of interleaved mode. In this paper, we identified performance evaluation items for each mode to analyze interleaved mode performance and proposed effective resource allocation methodology to achieve graceful performance degradation of each mode, focusing on detection range. We also proposed beam scheduling techniques for interleaved mode.

• KIPS Transactions on Software and Data Engineering
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• v.6 no.2
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• pp.103-116
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• 2017

In this paper, we present the design and implementation of a large-scale qualitative spatial reasoner, which can derive new qualitative spatial knowledge representing both topological and directional relationships between two arbitrary spatial objects in efficient way using Aparch Spark SQL. Apache Spark SQL is well known as a distributed parallel programming environment which provides both efficient join operations and query processing functions over a variety of data in Hadoop cluster computer systems. In our spatial reasoner, the overall reasoning process is divided into 6 jobs such as knowledge encoding, inverse reasoning, equal reasoning, transitive reasoning, relation refining, knowledge decoding, and then the execution order over the reasoning jobs is determined in consideration of both logical causal relationships and computational efficiency. The knowledge encoding job reduces the size of knowledge base to reason over by transforming the input knowledge of XML/RDF form into one of more precise form. Repeat of the transitive reasoning job and the relation refining job usually consumes most of computational time and storage for the overall reasoning process. In order to improve the jobs, our reasoner finds out the minimal disjunctive relations for qualitative spatial reasoning, and then, based upon them, it not only reduces the composition table to be used for the transitive reasoning job, but also optimizes the relation refining job. Through experiments using a large-scale benchmarking spatial knowledge base, the proposed reasoner showed high performance and scalability.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.8
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• pp.807-813
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• 2008

The gate-biases of the Doherty power amplifier are controlled to improve the linearity performance. The linearity improvement mechanism of the Doherty amplifier is the harmonic cancellation of the carrier and peaking amplifier at the output power combining point. However, it is difficult to cancel the harmonic power for the broader power range because the condition for cancelling is varied by power. For the linearity improvement, we have explored the linearity characteristic of the Doherty amplifier according to the input power and gate biases of the carrier and peaking amplifier. To extend the region of harmonic power cancellation, we have injected the proper gate bias to the carrier and peaking amplifier according to the input power levels. To validate the linearity improvement, the Doherty amplifier is designed using Eudyna 10-W PEP GaN HEMT EGN010MKs at 2.345 GHz and optimized to achieve a high linearity and efficiency at an average output power of 33 dBm, backed off about 10 dB from the $P_{1dB}$. In the experiments, the envelope tracking Doherty amplifier delivers a significantly improved adjacent channel leakage ratio performance of -37.4 dBc, which is an enhancement of about 2.8 dB, maintaining the high PAE of about 26 % for the WCDMA 1-FA signal at an average output power of 33 dBm. For the 802.16-2004 signal, the amplifier is also improved by about 2 dB, -35 dB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.2
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• pp.156-163
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• 2014

In this paper, a compact circularly polarized metamaterial patch antenna using cross aperture-coupled feed is proposed. The CP antenna utilizes the -1 mode that is induced by the composit right-left handed(CRLH) transmission line. Since the -1 mode has the same properties with the $TM_{010}$ mode of the conventional patch antenna, the circular polarization(CP) can be realized. If two orthogonal modes are excited with $90^{\circ}$ phase difference, the CP property can be obtained. In order to obtain two orthogonal modes and $90^{\circ}$ phase difference, 4 mushroom structures having the shape of square are employed. The width and length of the cross aperture are optimized through the design algorithm. The fabricated antenna is based on RT/duroid5880 substrate and the total area of the 4 mushroom is $0.25{\lambda}_0{\times}0.25{\lambda}_0$. The center frequency of the LHCP(Left-Handed Circular Polarization) antenna is measured as 1.622 GHz and circular polarization bandwidth(3 dB) is measured as 3 MHz. The center frequency of the RHCP(Right-Handed Circular Polarization) antenna is measured as 1.609 GHz and circular polarization bandwidth (3 dB) is measured as 3 MHz, respectively. The measured radiation efficiency of LHCP antenna is 61.1 % and the measured radiation efficiency of RHCP antenna is 54.5 %.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.23 no.8
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• pp.759-769
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• 2013

Electronic equipment has been applied to virtually every area associated with commercial, industrial, and military applications. Specifically, electronics have been incorporated into avionics components installed in aircraft. This equipment is exposed to dynamic loads such as vibration, shock, and acceleration. Especially, avionics components installed in a helicopter are subjected to simultaneous sine and random base excitations. These are denoted as sine on random vibrations according to MIL-STD-810F, Method 514.5. In the past, isolators have been applied to avionics components to reduce vibration and shock. However, an isolator applied to an avionics component installed in a helicopter can amplify the vibration magnitude, and damage the chassis, circuit card assembly, and the isolator itself via resonance at low-frequency sinusoidal vibrations. The objective of this study is to investigate the dynamic characteristics of an avionics component installed in a helicopter and the structural dynamic modification of its tray plate without an isolator using both a finite element analysis and experiments. The structure is optimized by dynamic loads that are selected by comparing the vibration, shock, and acceleration loads using vibration and shock response spectra. A finite element model(FEM) was constructed using a simplified geometry and valid element types that reflect the dynamic characteristics. The FEM was verified by an experimental modal analysis. Design parameters were extracted and selected to modify the structural dynamics using topology optimization, and design of experiments(DOE). A prototype of a modified model was constructed and its feasibility was evaluated using an FEM and a performance test.

• Composites Research
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• v.34 no.1
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• pp.35-46
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• 2021

This paper aims to reduce weight by replacing the reinforcements of the B-pillar used in vehicles with CFRP(Carbon Fiber Reinforced Plastics) and GFRP(Glass Fiber Reinforced Plastics) from the existing steel materials. For this, it is necessary to secure structural stability that can replace the existing B-pillar while reducing the weight. Existing B-pillar are composed of steel reinforcements of various shapes, including a steel outer. Among these steel reinforcements, two steel reinforcements are to be replaced with composite materials. Each steel reinforcement is manufactured separately and bonded to the B-pillar outer by welding. However, the composite reinforcements presented in this paper are manufactured at once through compression and injection processes using patch-type CFRP and rib-structured GFRP. CFRP is attached to the high-strength part of the B-pillar to resist side loads, and the GFRP ribs are designed to resist torsion and side loads through a topology optimization technique. Through structural analysis, the designed composite B-pillar was compared with the existing B-pillar, and the weight reduction ratio was calculated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.