• Title/Summary/Keyword: 위상검출기

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A 3.2Gb/s Clock and Data Recovery Circuit without Reference Clock for Serial Data Communication (시리얼 데이터 통신을 위한 기준 클록이 없는 3.2Gb/s 클록 데이터 복원회로)

  • Kim, Kang-Jik;Jung, Ki-Sang;Cho, Seong-Ik
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.46 no.2
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    • pp.72-77
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    • 2009
  • In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

PLL for Unbalanced Three-Phase Utility Voltage using Positive Sequence Voltage Observer (정상분 전압 관측기를 이용한 불평형 3상 전원의 PLL)

  • Kim, Hyeong-Su;Choi, Jong-Woo
    • The Transactions of the Korean Institute of Power Electronics
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    • v.13 no.2
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    • pp.145-151
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    • 2008
  • This paper proposes the PLL method using positive sequence voltage which is estimated by full-order state observer to find an accurate phase angle under the condition of unbalanced utility voltage. The proposed method uses the full-order state observer instead of existing method(APF All Pass Filter) to find a positive sequence of a utility voltage and this proposed method improves transient response of an estimated phase angle when a three-phase utility voltage becomes unbalanced. To compare proposed method withexisting method, experiments have been done for a phase angle detection of utility voltage when a three-phase utility voltage becomes unbalanced. Their results show that transient state response of proposed method is improved.

Design of a CMOS Frequency Synthesizer for FRS Band (UHF FRS 대역 CMOS PLL 주파수 합성기 설계)

  • Lee, Jeung-Jin;Kim, Young-Sik
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.28 no.12
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    • pp.941-947
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    • 2017
  • This paper reports a fractional-N phase-locked-loop(PLL) frequency synthesizer that is implemented in a $0.35-{\mu}m$ standard CMOS process and generates a quadrature signal for an FRS terminal. The synthesizer consists of a voltage-controlled oscillator(VCO), a charge pump(CP), loop filter(LF), a phase frequency detector(PFD), and a frequency divider. The VCO has been designed with an LC resonant circuit to provide better phase noise and power characteristics, and the CP is designed to be able to adjust the pumping current according to the PFD output. The frequency divider has been designed by a 16-divider pre-scaler and fractional-N divider based on the third delta-sigma modulator($3^{rd}$ DSM). The LF is a third-order RC filter. The measured results show that the proposed device has a dynamic frequency range of 460~510 MHz and -3.86 dBm radio-frequency output power. The phase noise of the output signal is -94.8 dBc/Hz, and the lock-in time is $300{\mu}s$.

An Adaptive Control of Symmetry Contribution Based Generalized Symmetry Transform (적응적 대칭기여도 제어 기반 일반화 대칭변환)

  • Jeon, Joon-Hyung;Lee, Seung-Hee;Park, Kil-Houm
    • Journal of Korea Multimedia Society
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    • v.17 no.2
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    • pp.208-217
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    • 2014
  • This paper propose an adaptive control of symmetry contribution based generalized symmetry transform. which can be controlled symmetry contribution according to the intensity orientation of two pixels. In the proposed method, we define the C-D(convergent and divergent)plane which represents convergence and divergence region of gradient pairs. and used the gaussian phase wight function, with respect to the distance from the gradient pair to an extreme point, in calculating the symmetry contribution. The proposed method can be detect the object more efficiently by adaptive controlling the cut-off frequency of the gaussian phase wight function. To evaluate a performance of the proposed method, we compare the proposed method and conventional GST method in various images including IR image. we prove that the proposed method have better performance in object detection.

Design of GPS L1 C/A Spoofing Signal Detection Algorithm (GPS L1 C/A 기만 신호 검출 기법 설계)

  • Lim, Soon;Lim, Deok-Won;Heo, Moon-Beom;Nam, Gi-Wook
    • Journal of Advanced Navigation Technology
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    • v.18 no.1
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    • pp.7-13
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    • 2014
  • In this paper, an effect on a GPS receiver by spoofing signal is analyzed and a GPS spoofing signal detection algorithm for GPS L1 C/A spoofing signal is proposed. A proposed detection algorithm monitors the correlation function distortion by the spoofing signal. If detected distortion is over a detection threshold, we can determine that the spoofing signal is received. The detection threshold is calculated from the statistical characteristics of a thermal noise. For verifying the suggested algorithm, a MATLAB-based simulation platform is implemented. This platform has functionalities to track GPS signal and measure the correlation values. By using this platform, the correlation function distortion by spoofing signal is observed. Also a performance of the algorithm proposed in this paper is applied and confirm the detection of a spoofing signal.

A 166MHz Phase-locked Loop-based Frequency Synthesizer (166MHz 위상 고정 루프 기반 주파수 합성기)

  • Minjun, Cho;Changmin, Song;Young-Chan, Jang
    • Journal of IKEEE
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    • v.26 no.4
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    • pp.714-721
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    • 2022
  • A phase-locked loop (PLL)-based frequency synthesizer is proposed for a system on a chip (SoC) using multi-frequency clock signals. The proposed PLL-based frequency synthesizer consists of a charge pump PLL which is implemented by a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage controlled oscillator (VCO), and a frequency divider, and an edge combiner. The PLL outputs a 12-phase clock by a VCO using six differential delay cells. The edge combiner synthesizes the frequency of the output clock through edge combining and frequency division of the 12-phase output clock of the PLL. The proposed PLL-based frequency synthesizer is designed using a 55-nm CMOS process with a 1.2-V supply voltage. It outputs three clocks with frequencies of 166 MHz, 83 MHz and 124.5MHz for a reference clock with a frequency of 20.75 MHz.

Design of a 2.5GHz Quadrature LC VCO with an I/Q Mismatch Compensator (I/Q 오차 보정 회로를 갖는 2.5GHz Quadrature LC VCO 설계)

  • Byun, Sang-Jin;Shim, Jae-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.2
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    • pp.35-43
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    • 2011
  • In this paper, an analysis on I/Q mismatch characteristics of a quadrature LC VCO(Voltage controlled oscillator) is presented. Based on this analysis, a new I/Q mismatch compensator is proposed. The proposed I/Q mismatch compensator utilizes an amplitude mismatch detector rather than the conventional phase mismatch detector requiring much more wide frequency bandwidth. To verify the proposed circuit, a 2.5GHz quadrature LC VCO was designed in a $0.18{\mu}m$ CMOS process and tested. Test results show that an amplitude mismatch detector achieves similar I/Q mismatch compensation performance as that of the conventional phase mismatch detector. The I/Q mismatch compensator consumes 0.4mA from 1.8V supply voltage and occupies $0.04mm^2$.

The Analysis of Amplitude and Phase Image for Acoustic Microscope Using Quadrature Technique (쿼드러춰 방식에 의한 초음파현미경의 진폭과 위상영상 분석)

  • Kim, Hyun;Jun, Kye-Suk
    • The Journal of the Acoustical Society of Korea
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    • v.18 no.3
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    • pp.55-61
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    • 1999
  • In this study, we have constructed the acoustic microscope using quadrature technique and analyzed the relative variation of image intensity and the quality of image by reconstructing the amplitude and phase image for surface defects with tiny hight variation. In this experiment, we have constructed the scanning acoustic microscope using the focused transducer with 3㎒ center frequency and the quadrature detector. And we have fabricated aluminum samples with round defects whose depth is different and reconstructed the amplitude and phase images for the samples. One sample has round defects with 2㎜ diameter and 100㎛ depth and the other has round defects with 4㎜ diameter and 5㎜ depth. In the result of line scanning for the sample with 100㎛ round defects, it has been shown that the variation rate of amplitude image intensity is 7% and the variation rate of phase image intensity is 89%. The phase image has better contrast than amplitude image for the sample. In contrast to this, the amplitude image has better contrast than phase image for the sample with 5㎜ depth's defects. Accordingly there is big difference between amplitude image and phase image for depth variation of defects whose boundary is 1 wavelength. Consequently the acoustic microscope using quadrature detector can be evaluated efficiently more than using envelope detector, for detecting defects which have height variation less than 1 wavelength. And also the phase image and the amplitude image can be used for detecting defects of tiny height variation with complimentary relation.

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Performance Comparison of Phase Detectors for the Synchronization Analysis of Electroencephalographic Signal (뇌파신호의 동기해석을 위한 위상검출기의 성능비교)

  • Kim, HyeJin;Lee, JeeEun;Yoo, Sun K.
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.12
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    • pp.277-284
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    • 2013
  • The analysis of phase synchronization characteristics from EEG signals is important for the understanding of information processing functionality in the brain network. In this paper, wavelet transformation(WT), Hilbert tansformation (HT), complex demodulation (CD) methods having time localization characteristics were applied to real evoked potential data and noise added simulation data with center frequencies corresponding to EEG bands for the estimation performance analysis of phase offset, phase changing point, and interband crosstalk. The WT is the best both in ${\delta}$, ${\theta}$, and ${\alpha}$ band signal decomposition, and in analyzing phase synchronization performance. The CD can be efficiently used in changing point detection under tolerant noise condition because of its abrupt performance degradation over noise endurance level. From experimental observations, the WT is the most suitable in phase synchronization application of EEG signal, and the CD can be affordable in restricted application such as changing point detection for higher bands than ${\delta}$. Particularly, WT and CD can be used to detect the changing instant of brain function by indirectly estimating the phase changing point.

A Phase Detection Method in Grid-Connected Converters using Oberber (관측기를 이용한 계통 연계형 컨버터에서 위상검출 방법에 대한 연구)

  • Kim, Young-Chun;Cho, Moon-Tack;Song, Ho-Bin;Kim, Ok-Hwan;Hong, Soon-Jik;Joo, Hae-Jong;Lee, Euy-Soo
    • Proceedings of the KAIS Fall Conference
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    • 2012.05b
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    • pp.796-799
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    • 2012
  • 직류전원장치에 사용되는 계통연계형 컨버터는 전원의 위상을 기준으로 제어되어야 하므로 하드웨어 또는 소프트웨어적인 다양한 방법들이 사용되고 있다. 이러한 방법들은 복잡하거나 노이즈에 의한 오동작 등의 위해요소를 내포하고 있다. 이에 본 논문에서는 관측기를 이용하여 전원의 주파수 변동에도 사용할 수 있는 강인한 위상점지 방법에 대해 제안하고 실험을 통해 입증하였다.

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