• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.2
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• pp.162-169
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• 2011

The flight control system utilize RSS(Relaxed Static Stability) criteria in both longitudinal axes to achieve performance enhancements and improve stability. The aircraft using digital flight-by-wire flight control system receives aircraft flight conditions such as pitch, roll and yaw rate, normal acceleration from RSA(Rate Sensor Assembly) and ASA(Acceleration Sensor Assembly). These sensors has permissible measurement error related to system safety of an aircraft but, unexpected flight motions are happened by sensing errors such as offset, noise and etc. The unexpected pitch down tendency occurred by ASA sensor bias in 1g level flight with pilot hands-off. This paper addresses the design and verification of flight control law to improve of pitch down or up tendency caused by ASA sensor bias. The result of analysis and flight test reveals that pitch down tendency can be improved by pitch attitude feedback system.

• Proceedings of the Korea Inteligent Information System Society Conference
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• 2000.11a
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• pp.317-324
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• 2000

주기적인 연관규칙은 타겟데이터베이스를 일정 단위시간으로 나누었을 때 연관규칙이 만족하는 구간이 일정한 주기마다 발생하는 패턴을 탐색하는 방법이다. 하지만, 이 방법은 엄격한 주기를 가지도록 하여 실제 데이터에 그대로 적용하기가 어려웠다. 예를 들이 편의점 데이터에서 매일 오전 7시-8시 사이에 주기적으로 발생하는 연관규칙을 발견할 때, 이러한 연관규칙을 주기적인 연관규칙이라고 한다. 하지만, 실제 데이터에서는 날씨와 같이 사람의 행동에 영향을 미치는 다른 요인 때문에 항상 일정한 주기를 가지는 연관규칙을 찾기는 어렵다. 본 논문에서는 주기가 일정하지 않은 연관규칙을 찾기 위해서 연관규칙의 주기성을 허용 오차를 포함하며 재정의하고, 오차를 허용하기 위한 탐색 알고리즘을 보완하였다. 반면에, 오차를 허용함으로써 오차를 허용하지 않는 경우보다 더 많은 주기성을 찾을 수 있을 뿐만 아니라, 동일한 주기를 가지지만 오프셋이 다른 여러 개의 비슷한 주기가지 찾게 되어 사용자가 의미 있는 연관규칙을 찾는데 방해가 된다. 본 논문에서는 이를 해결하기 위해서 오차를 허용하는 주기적 연관규칙의 오차의 정도를 측정하기 위한 단위로 집중도(intensity)와 경향성(tendency)을 제안한다. 주기적 연관규칙이 매 주기마다 정확한 세그먼트에 나타나는 정도를 나타내는 집중도와, 최소 평균오차를 의미하는 경향성을 이용하여 유사한 주기들 중에서 대표주기만을 찾을 수 있도록 한다. 또한, 오차를 허용하는 주기적 연관규칙에서 오차가 주로 발생하는 패턴을 분석함으로써 고객들의 수요 경향성을 더 잘 파악할 수 있다. 예를 들어, 평소에는 매일 오진 7시∼8시에 나타나던 연관성이 지각하는 사람들이 같은 월요일에는 1시간 늦은 8시∼9시에 나타난다는 오타 정보까지 파악할 수 있다. 이러한 월요일마다 1시간 늦게 나타나는 오차의 경향성을 나타내는 오차 주기(error cyc1e)를 이용함으로써 고객들의 수요의 경향성을 좀 더 세밀한 부분까지 파악할 수 있게 해 준다.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.1
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• pp.65-73
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• 2007

This paper presents an on-line correction method of current measurement errors for a pure-integration-based flux estimation down to 1-Hz stator frequency. An observer-based approach is taken as one possible solution of eliminating the dc offset and the negative sequence component of unbalanced gains in the synchronous coordinate. At the same time, the positive sequence component estimation is performed by creating an error signal between a motor model reference and an estimated q-axis rotor flux established by a permanent magnet (PM) in the synchronous coordinate. The compensator utilizes a PI controller that controls the error signal to zero. The proposed technique further contains a residual error compensator to completely eliminate miscellaneous disturbances in the estimated flux. The developed algorithm has been implemented on a 1.1-kW permanent magnet synchronous motor (PMSM) drive to confirm the effectiveness of the proposed scheme.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.169-177
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• 2015

This paper proposes a hardware architecture for an efficient SAO(Sample Adaptive Offset) with low area for HEVC(High Efficiency Video Coding) encoder. SAO is a newly adopted technique in HEVC as part of the in-loop filter. SAO reduces mean sample distortion by adding offsets to reconstructed samples. The existing SAO requires a great deal of computational and processing time for UHD(Ultra High Definition) video due to sample by sample processing. To reduce SAO processing time, the proposed SAO hardware architecture processes four samples simultaneously, and is implemented with a 2-step pipelined architecture. In addition, to reduce hardware area, it has a single architecture for both luma and chroma components and also uses optimized and common operators. The proposed SAO hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 190k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 200MHz, it can support 4K UHD video encoding at 60fps in real time, but operates at a maximum of 250MHz.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.37 no.1
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• pp.97-103
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• 2013

This study proposes a path generation technique for simultaneous five-axis driving for ball bar measurement, which is equivalent to cone frustum machining as mentioned in the NAS979 standard. The technique is generalized for a 3D circular path, and it is applicable to all machine tools regardless of their structural configurations. A mathematical machine input model that consists of a five-axis machine tool, ball-bar measurement and conical path information as inputs is presented for easy NC code generation, simulation for various test conditions, and a measurement test. The movement range of rotary axes, which depends on various conditions, is mathematically analyzed based on the proposed conical path model. Moreover, the effect of the movement range on various conditions (apex angle and inclination angle, ball bar tilting acceptance angle, offset position of workpiece ball, etc.) is analyzed.

• Journal of Fashion Business
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• v.20 no.4
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• pp.153-171
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• 2016

With the advent of smart clothing for health care and sports, the sophisticated designs with curved seams are drawing attention. One of the problems in those clothing is to determine the design curves in 2D pattern, such that it corresponds to the lines on the intended 3D body. Moreover, the difficulty increases when the original pattern needs to be changed for various sizes and body types. We compare two methods of pattern enlargement in this paper: one is the offset/projection type, and the other is the split grading type. For the enlarged pattern with offset/projection type, the 3D surface offset was first adopted to transform the standard lower body to the target larger size; next, the design lines were projected to the new 3D surface, following which the 3D pattern was developed from the newly transformed 3D surface. In the second method, the enlarged pant patterns were developed by the split grading method. Here, a 3D pattern was developed from the initial body, and then enlarged to the target size by the conventional split grading method. Two feminine pants patterns were examined by 3D virtual fitting. We observed that the 3D offset/projection pants pattern was well fitted, having an evenly distributed surplus, as compared with the sample developed using the split grading method. The difference between the two patterns were apparent at the location where several curved lines merged.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.9
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• pp.2369-2378
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• 2009

In this paper, we implement measurement functionality for performance measurement of the GSM (Global System for Mobile Communication) terminal by using software. Generally speaking, the receiving algorithms in normal modems cannot be used directly to the measurement system due to the lack of the algorithm accuracy. In this paper, we propose the new receiver algorithm for precise GSM signal measurements. In the receiving algorithm, 2-stage (coarse stage, fine stage) parameters estimation (symbol-timing, frequency offset, carrier phase) scheme is used. To improve the estimation accuracy, we increase the number of the received signal samples by interpolation. The proposed GSM signal measurement algorithm can be used for verifying the hardware measurement system. In addition, the proposed algorithm can be used for the commercial system through code execution speed optimization.

• Journal of Advanced Navigation Technology
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• v.17 no.6
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• pp.705-711
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• 2013

In this paper, we present a low-complexity non-coherent demodulation algorithm and hardware architecture for LR-WPAN systems which can support the variable data rate for various applications. The need for LR-WPAN systems that can support the variable data rate is increasing due to the emergence of various sensor applications. Since the existing symbol based double correlation (SBDC) algorithm requires the increase of complexity to support the variable data rate, we propose the sample based double correlation (SPDC) algorithm which can be implemented without the increase of complexity. The proposed non-coherent demodulator was designed by verilog HDL and implemented with FPGA prototype board.

• Journal of Advanced Navigation Technology
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• v.23 no.5
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• pp.392-399
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• 2019

In this paper, we have studied wireless time division duplex(TDD) time synchronization technique considering the propagation delay between mobile vehicles. The existing IEEE 1588 precision time protocol(IEEE 1588 PTP) algorithm was applied and the time synchronization between the two nodes was achieved through the propagation delay and clock offset time correction calculated between master slave nodes during wireless TDD communication. The time synchronization process and procedure of IEEE 1588 PTP algorithm were optimized, thereby reducing the propagation delay error sensitivity for real-time moving vehicles. The sync flag signal generated through the time correction has a time synchronization accuracy of max +252.5 ns within 1-symbol(1.74 M symbol/sec, ${\pm}287.35ns$) through test and measurement, and it was confirmed that the time synchronization between master slave nodes can be achieved through sync flag signal generated during GPS disturbance.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.3
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• pp.417-422
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• 2021

In this paper, a ZQ calibration using a time domain comparator is proposed. The proposed comparator is designed based on VCO, and an additional clock generator is used to reduce power consumption. By using the proposed comparator, the reference voltage and the PAD voltage were compared with a low 1 LSB voltage, so that the additional offset cancelation process could be omitted. The proposed time domain comparator-based ZQ calibration circuit was designed with a 65nm CMOS process with 1.05V and 0.5V supply voltages. The proposed clock generator reduces power consumption by 37% compared to a single time domain comparator, and the proposed ZQ calibration increases the mask margin by up to 67.4%.