• Journal of KIISE:Computer Systems and Theory
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• v.26 no.5
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• pp.620-626
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• 1999

캐리-세이브 가산기는 (CSA)는 실제 산업체에서 회로를 설계할 때 연산수식의 계산을 빠르게 처리하기위해 가장 많이 사용되는 구성요소들 가운데 하나이다. [3]의 자료에 의하면 실제 회로 설계에서 나오는 전형적인 연산식에 CSA를 이용했을 때 그렇지 않은 경우보다 최대 54%의 연산처리속도와 42%의 회로 면적 향상을 갖는다고 보고하고 있다. 그러나, 이는 그 연산식이 하나의 설계 블록(sub-design)에 포함되어 있다는 전제하에 도출된 것이다. 회로 설계 규모와 복잡도가 큰 응용이 많아지는 상황에서 설계 블록단위의 계층적 설계는 필수적인 추세이므로, CSA를 이용한 회로 최적화를 실현하기위해서는 설계 블록들간에 걸쳐있는 연산식에 대한 CSA 최적화 또한 매우 중요한 문제이다. 이를 해결하기위해서 이 논문에서는 auxiliary port라는 개념을 이용하여 설계 블록들간의 연산식에 대한 CSA 최적화 방법을 제안한다. 실제 실험에서 우리가 제안한 기법은 회로의 전체적인 영역에 걸쳐 CSA를 적용하는 데 매우 효과적이었으며, 이 기법을 적용하지 않고 얻은 CSA 최적화 회로와 비교했을 때 회로에서의 연산식 계산속도와 그 회로 면적이 상당히 향상되었음을 확인하였다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.05a
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• pp.45-45
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• 2004

B-rep 기반의 솔리드 복원 기법은 비교적 복잡한 물체의 경우에도 복원이 잘 되지만, 후보면의 수가 증가함에 따라 탐색 공간 및 시간이 기하급수적으로 늘어나는 단점이 있다. 빈번한 조합 탐색과 복잡한 기하 연산으로 인해 도면이 복잡해질수록 복원 효율성이 떨어지고, 모호성이 발생하는 문제가 있다. 그러나, 이차 곡면을 포함하는 복잡한 물체에 대해서도 복원이 가능하므로 복원 대상 범위가 넓다고 할 수 있다. CSG 기반의 솔리드 복원 기법은 세 투영면에서 돌출 시킨 각각의 솔리드를 서로 교차시켜서 3차원 물체를 복원하는 방법으로, 복잡한 조합 탐색이나 기하 연산 작업을 하지 않게 때문에 비교적 효율적인 복원이 가능하다.(중략)

• Journal of Advanced Navigation Technology
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• v.15 no.2
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• pp.213-220
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• 2011

In this paper, the channel preprocessor with an area-efficient architecture is proposed for the MIMO symbol detector which can support four transmit and receive antennas. The proposed channel preprocessor can shrink the channel dimension to reduce the hardware complexity of the MIMO symbol detector. Also, the proposed channel preprocessor is implemented with very low complexity by using QR decomposition (QRD) and log-number system (LNS). By applying QRD and LNS to the nulling matrix calculation block, the numbers of matrix-multiplications and matrix-divisions are decreased and thus the complexity of the proposed channel preprocessor is significantly reduced. The proposed channel preprocessor was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.13um CMOS standard cell library. With the proposed channel preprocessor, the number of logic gates for channel preprocessor is reduced by 20.2% compared with the conventional architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.47-52
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• 2009

H.264 video coding standard is widely used due to the high compression rate and quality. The motion compensation is the most time-consuming and complex unit in the H.264 decoder. The performance of the motion compensation is determined by the calculation of pixel interpolation and management of the reference pixels. The reference pixels read from external memory using efficient memory management for data reuse is necessary along with the high performance interpolators. We propose the architecture of a motion compensation unit for H.264 decoders. It is composed of 2-dimensional circular register files, a motion vector predictor and high performance interpolators with low complexity. The 2-dimensional circular register files reuse reference pixel data as much as possible, and feed reference pixel data to interpolators without any latency and complex logic circuits. We design a motion compensation unit and a intra-prediction unit and integrate them into a prediction unit and verify the operation and the performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.9
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• pp.1786-1792
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• 2015

Random linear network coding (RLNC) is widely employed to enhance the reliability of wireless multicast. In RLNC encoding/decoding, Galois Filed (GF) arithmetic is typically used since all the operations can be performed with symbols of finite bits. Considering the architecture of commercial computers, the complexity of arithmetic operations is constant regardless of the dimension of GF m, if m is smaller than 32 and pre-calculated tables are used for multiplication/division. Based on this, we show that the complexity of RLNC inversely proportional to m. Considering additional overheads, i.e., the increase of header length and memory usage, we determine the practical value of m. We implement RLNC in a commercial computer and evaluate the codec throughput with respect to the type of the tables for multiplication/division and the number of original packets to encode with each other.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.2
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• pp.287-297
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• 2019

When cryptographic algorithms are implemented to provide countermeasures against the side-channel analysis, designers frequently employ the combined countermeasures between the first-order masking scheme and hiding schemes. Their combination can be enough to offer security and efficiency. However, if dummy operations can be distinguished from real operations, an attacker can extract the secret key with lower complexity than the intended attack complexity by the designer inserting the dummy operations. In this paper, we categorize types of variables used in a dummy operation when C language is employed. Then, we present the novel vulnerability that can distinguish dummy operations for all cases where the hiding schemes are applied using different types of variables. Moreover, the countermeasure is provided to prevent the novel vulnerability.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.6C
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• pp.634-641
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• 2009

The goal of OSIC-series detection methods is to approach the ML performance with feasible complexity. However, since they sometimes suffer from the empty vector problem, they can not achieve the soft-output ML performance or many candidate vectors are required to achieve the soft-output ML performance. In this paper, we propose the novel detection method, which can generate the reliable soft-outputs without suffering from empty vector problem. The proposed detector can approach the near soft-output ML performance as well as hard-output. Further, the complexity study shows that the proposed detection method has the lowest complexity compared to the other detectors having the near ML performance.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.2
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• pp.335-344
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• 2016

It is known that power analysis is one of the most powerful attack in side channel analysis. Among power analysis single trace attack is widely studied recently since it uses one power consumption trace to recover secret key of public cryptosystem. Recently Sim et al. proposed new exponentiation algorithm for RSA cryptosystem with higher attack complexity to prevent single trace attack. In this paper we analyze the vulnerability of exponentiation algorithm described by Sim et al. Sim et al. applied message blinding and random exponentiation splitting method on $2^t-ary$ for higher attack complexity. However we can reveal private key using information exposed during pre-computation generation. Also we describe modified algorithm that provides higher attack complexity on collision attack. Proposed algorithm minimized the reuse of value that are used during exponentiation to provide security under single collision attack.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12A
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• pp.1387-1395
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• 2004

Turbo decoder inherently requires large memory and intensive hardware complexity due to iterative decoding, despite of excellent decoding efficiency. To decrease the memory space and reduce hardware complexity, various design issues have to be discussed. In this paper, various design issues on Turbo decoder are investigated and the tradeoffs between the hardware complexity and the performance are analyzed. Through the various simulations on the fixed-length analysis, we decided 5-bits for the received data, 6-bits for a priori information, and 7-bits for the quantization state metric, so the performance gets close to that of infinite precision. The MAX operation which is the main function of Log-MAP decoding algorithm is analyzed and the error correction term for MAX* operation can be efficiently implemented with very small hardware overhead. The size of the sliding window was decided as 32 to reduce the state metric memory space and to achieve an acceptable BER.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.11
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• pp.663-674
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• 2003

Bump mapping is a technique that represents the detailed parts of the object surface, such as a perturberance of the skin of a peanut, using the geometry mapping without complex modeling. However, the hardware implementation for bump mapping is considerable, because a large amount of per pixel computation, including the normal vector shading, is required. In this paper, we propose a new bump mapping algorithm using the polar coordinate system and its hardware architecture. Compared with other existing architectures, our approach performs bump mapping effectively by using a new vector rotation method for transformation into the reference space and minimizing illumination calculation. Consequently, our proposed architecture reduces a large amount of computation and hardware requirements.