• Title/Summary/Keyword: 연산증폭기

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스위치-연산증폭기 신호처리 시스템 구현을 위한 새로운 1.2V class-AB push-pull 출력단 회로의 설계

  • Gwon, O-Jun;U, Seon-Bo;Gwak, Gye-Dal
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.637-638
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    • 2006
  • A novel 1.2V class-AB output stage for the SW-OpAmp technique was presented. By using current mirrors and simple current extraction circuits, the proposed circuit boosts DM signal currents while eliminates CM ones to perform class-AB operation. Hspice simulation results verify the versatility of the proposed circuit technique.

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Study on a grounded inductor simulated by the use of the operational amplifier (연산증폭기를 이용한 접지형 인덕터의 구성에 관한 연구)

  • 김성수;공남수
    • 전기의세계
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    • v.28 no.9
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    • pp.35-40
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    • 1979
  • A grounded inductor is proposed which contains only one resistor and operational amplifier. The circuit uses the inherent frequency dependent characteristic of an amplifier to simulate the inductor. A parallel resonance circuit is constructed with the proposed circuit. It has been proved by the experimental results of the resonant circuit that the proposed circuit is equivalent to the grounded lossy inductor. The lossy inductor is imbedded in a passive bandstop prototype, and the resultant characteristic curve has been verified by the experiment.

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High Gain and High Efficiency Class-E Power Amplifier Using Controlling Drain Bias for WPT (드레인 조절회로를 이용한 무선전력전송용 고이득 고효율 Class-E 전력증폭기 설계)

  • Kim, Sanghwan;Seo, Chulhun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.9
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    • pp.41-45
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    • 2014
  • In this paper, a high-efficiency power amplifier is implemented by using a drain bias control circuit operated at low input power for WPT(Wireless Power Transfer). Adaptive bias control circuit was added to high-efficiency class-E amplifier. It was possible to obtain the overall improvement in efficiency by adjusting the drain bias at low input power. The proposed adaptive class-E amplifier is implemented by using the input and output matching network and serial resonant circuit for improvement in efficiency. Drain bias control circuit consists of a directional coupler, power detector, and operational amplifier for adjusting the drain bias according to the input power. The measured results show that output powers of 41.83 dBm were obtained at 13.56 MHz. At this frequency, we have obtained the power added efficiency(PAE) of 85.67 %. It was confirmed increase of PAE of an average of 8 % than the fixed bias from the low input power level of 0 dBm ~ 6 dBm.

A Novel Third-Order Cascaded Sigma-Delta Modulator using Switched-Capacitor (스위치형 커패시터를 이용한 새로운 형태의 3차 직렬 접속형 시그마-델타 변조기)

  • Ryu, Jee-Youl;Noh, Seok-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.1
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    • pp.197-204
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    • 2010
  • This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented m a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage. The 1% settling time of the opamp is measured to be 560 ns with load capacitance of 16 pF. The experimental testing of the sigma-delta modulator with bit-stream inspection and analog spectrum analyzing plot is performed. The die size is $1.9{\times}1.5\;mm$.

Bistable Multivibrator Using Second Generation Current Conveyor and Its Application to Resistive Bridge Sensor (2세대 전류 컨베이어를 이용한 쌍안정 멀티바이브레이터 설계 및 저항형 브리지 센서에의 응용)

  • Chung, Won-Sup;Park, Jun-Min
    • Journal of IKEEE
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    • v.23 no.2
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    • pp.636-641
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    • 2019
  • A simple resistance deviation-to-time period converter is proposed for interfacing resistive half-bridge sensors. It consists of two 2nd generation current conveyors(CCIIs). The proposed converter has simpler circuit configuration than the conventional converters using operational amplifiers or operational transconductance amplifiers(OTAs). The proposed converter was simulated using CCII implemented with AD844 IC chips. The simulation results show that the converter has a conversion sensitivity of $0.01934ms/{\Omega}$ over a range of $100-500{\Omega}$ resistance deviations and a linearity error less than ${\pm}0.002%$.

TID and SEL Testing on OP-Amp. of DC/DC Power Converter (DC/DC 컨버터용 OP-Amp.의 TID 및 SEL 실험)

  • Lho, Young Hwan
    • Journal of the Korean Society of Radiology
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    • v.11 no.3
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    • pp.101-108
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    • 2017
  • DC/DC switching power converters are commonly used to generate a regulated DC output voltage with high efficiency. The advanced DC/DC converter uses a PWM-IC with OP-Amp. (Operational Amplifier) to control a MOSFET (metal-oxide semiconductor field effect transistor), which is a switching component, efficiently. In this paper, it is shown that the electrical characteristics of OP-Amp. are affected by radiations of ${\gamma}$ rays using $^{60}Co$ for TID (Total Ionizing Dose) testing and 5 heavy ions for SEL (Single Event Latch-up) testing. TID testing on OP-Amp. is accomplished up to the total dose of 30 krad, and the cross section($cm^2$) versus LET($MeV/mg/cm^2$) in the OP-Amp. operation is evaluated SEL testing after implementation of the controller board.

HVPM model and circuit implementation for generating hyperchaotic signals (하이퍼카오스 신호발생을 위한 HVPM 모델 및 회로 구현)

  • 이익수;이동록;여지환;송규익
    • Proceedings of the IEEK Conference
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    • 2000.11c
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    • pp.17-20
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    • 2000
  • 본 논문에서는 복잡한 카오스 신호를 발생시키는 HVPM(hyperchaotic volume preserving maps) 모델과 HVPM 모델의 구현회로를 제안한다. 랜덤 한 카오스 신호를 발생시키기 위하여 3차원 이산시간(discrete-time) 연산과 비선형 사상(maps)으로 모듈러(modulus) 함수를 이용하여 하이퍼카오스 신호를 발생시킨다. 그리고 HVPM 모델은 여러 가지 시스템 파라미터들을 변화시키면 다양한 카오스 신호를 발생시킬 수 있으며, 출력되는 카오스 신호는 비주기성을 갖게 된다. 이러한 특징을 갖는 HVPM 모델의 회로 구현을 위하여 2단 N형의 함수를 CMOS와 선형 연산증폭기 및 비교기를 이용하여 보드상에서 구현하여, 다양한 하이퍼카오스 신호를 확인할 수 있었다.

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Design of Frequency to Analog-Voltage Converter (주파수-아날로그 전압 변환 회로의 설계)

  • Choi, Jin-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.5
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    • pp.1119-1124
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    • 2011
  • The operation of current conveyor circuit is similar to an operational amplifier and a current conveyor circuit has the characteristics such as good linearity and stability. In this paper, a frequency-to-voltage converter circuit is designed by using a current conveyor circuit. The supply voltage is 5volts and the designed circuit is simulated by HSPICE. The range of the input frequency is from 4kHz to 200kHz. From the simulation results the error of the output voltages is less than from -1.3% to +2.5% compared to the calculated values.

Investigation of miximum permitted error limits for second order sigma-delta modulator with 14-bit resolution (14 비트 분해능을 갖는 2차 Sigma-Delta 변조기 설계를 위한 구성요소의 최대에러 허용 범위 조사)

  • Cho, Byung-Woog;Choi, Pyung;Sohn, Byung-Ki
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.23 no.5
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    • pp.1310-1318
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    • 1998
  • Sigma-delta converter is frequently used for conyerting low-frequency anglog to digital signal. The converter consists of a modulator and a digital filer, but our work is concentrated on the modulator. In this works, to design second-order sigma-dalta modulator with 14bit resolution, we define maximumerror limits of each components (operational smplifier, integrator, internal ADC, and DAC) of modulator. It is first performed modeling of an ideal second-order sigma-delta modulator. This is then modified by adding the non-ideal factors such as limit of op-amp output swing, the finit DC gain of op-amp slew rate, the integrator gian error by the capacitor mismatch, the ADC error by the cmparator offset and the mismatch of resistor string, and the non-linear of DAC. From this modeling, as it is determined the specification of each devices requeired in design and the fabrication error limits, we can see the final performance of modulator.

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A Study on Performance Improvement of Detecting Current of the Norton Amplifier (노튼 증폭기의 전류검출성능 개선에 관한 연구)

  • Kwon, Sung-Yeol;Lee, Hyun-Chang;Lee, Kyu-Tae
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.18 no.3
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    • pp.185-191
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    • 2018
  • In this paper, an improved Norton amplifier is proposed and the problems caused by the current input in the Norton amplifier, which has advantages in current transmission, are analyzed. The output of the voltage follower consisting of an operational-amplifier with constant output voltage characteristics is used as an input terminal of the proposed circuit. It is configured to detect the power supply current passing through the voltage follower and extract the current from the input terminal. The performance of the improved Norton amplifier is verified at experiment according to the input current. The results are compared with conventional Norton amplifier. Consequently, the input offset voltage, which is a problem in the conventional Norton amplifier, was removed in the proposed circuit. In addition, the average error of the output voltage with respect to the input current was reduced to 4.755%. It is verified that the characteristics of the proposed circuit are improved.