• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.12
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• pp.1698-1704
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• 2018

This paper presents a implementation of a chaotic Lorenz system for data secure communication applications. Here we have used PIC18F family-based microcontroller to generate the chaotic signal, and simulated waveform patterns confirm that the chaotic behavior of the microcontroller based discrete time chaotic Lorenz system. There are three R-2R ladder type A/D converters have been implemented for conversion of direct microcontroller digital output into analog waveform, utilizing this specific microcontroller relevant to this experiment work, microcontroller ports B, C and D have been utilized for its time waveform outputs X, Y and Z respectively. XC8 compiler used for the compilation of the program. MATLAB and PROTEUS software platforms are used for simulation. Finally, chaotic time wave forms, 2D chaotic attractors were obtained and secure communication analog waveforms were also verified by experimental measurement.

• Journal of IKEEE
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• v.26 no.2
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• pp.299-305
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• 2022

Analog-digital converter (ADC) should be one of the most important blocks that convert various physical signals to digital ones for signal processing in the digital signal domain. As most operations of the analog circuit for sensor signal processing have been replaced by digital circuits, high-resolution performance is required for ADC. In addition, low-power must be the critical issue in order to extend the battery time of mobile system. The existing integrating sigma-delta ADCs has a characteristic of high resolution, but due to its low supply voltage condition and advanced technology, circuit error and corresponding resolution degradation of ADC result from the finite gain of the operational amplifier in the integrator. Buffer compensation technique can be applied to minimize gain errors, but there is a disadvantage of additional power dissipation due to the added buffer. In this paper, incremental signal-delta ADC is proposed with buffer switching scheme to minimize current and igh-pass bias circuit to improve the settling time.

• Journal of IKEEE
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• v.12 no.3
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• pp.167-171
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• 2008

A bridge resistance deviation-to-frequency (BRD-to-F) converter is presented for interfacing resistive sensor bridges. It consists of a linear operational transconductance amplifier (LOTA), a current-controlled oscillator (CCO). The prototype converter was simulated using commercially available discrete components. The result shows that the converter has a conversion sensitivity amounting to 16.90 kHz/${\Omega}$ and a linearity error less than ${\pm}$0.03 %.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.75-84
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• 2001

Due to the high density of integration in current integrated circuit layouts, circuit elements must be designed to minimize the effect of parasitic elements and thereby minimize the factors which can degrade circuit performance. Thus, before making a chip, circuit designers should check whether the extracted netlist is correct, and verify from a simulation whether the circuit performance satisfies the design specifications. In this paper, we propose a new block disassembly technique which can extract the geometric parameters of stacked MOSFETs and the distributed RCs of layout blocks. After applying this to the layout of a folded-cascode CMOS operational amplifier, we verified the connectivity and the effect of the components by simulating the extracted netlist with HSPICE.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.505-508
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• 2000

본 논문에서는 16채널 혹은 8채널의 센서를 통해 들어오는 저주파대역의 아날로그 신호를 수집하고. 수집된 데이터를 실시간으로 처리하기 위한 고속의 신호처리 기능이 결합된 통합 DSP (Digital Signal Processor)시스템을 구현하였다. 구현된 시스템은 휴대가 용이하도록 소형으로 설계되어 있으며 노트북 등의 이동형 장비에 활용되도록 USB 인터페이스를 채택하였으며, 장치간의 네트워크 구성이 가능하도록 Ethernet 인터페이스를 추가하였다 Digital Signal Processor는 Texas Instrument 사의 TMS320C6701 부동소수점 연산방식의 고성능 DSP를 사용하여 16채널의 실시간 신호 분석이 가능하게 하였으며, ICP 센서 구동용 전류 공급부를 내장하여 센서 선택의 폭을 넓히었고, programmable gain amplifier인 PGA202증폭기를 사용하여 입력신호가 작을 경우 최대 1000배, 즉 60dB까지 입력신호를 증폭하여 수집 및 분석할 수 있다. 200kSPS의 샘플링 레이트와 16bit resolution을 가지는 AD976 A/D converter를 사용하여 채널당 0～6kHz의 신호대역폭을 가지며,differential 입력시 8 채널,single ended 입력시 16 채널의 입력 신호의 수집 및 분석이 가능하다. Windows 응용프로그램에서는 사용자가 원하는 입력신호 및 스펙트럼 실시간 분석, 입력신호 기록 및 저장, RPM 측정 및 분석, 외부 트리거 및 레벨 트리거를 이용한 입력신호 제어와 수집된 데이터를 바탕으로 원하는 제어가 가능한 응용프로그램 제작에 활용될 라이브러리가 포함된다.

• Journal of IKEEE
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• v.20 no.4
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• pp.428-431
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• 2016

Power semiconductor devices had been producted with bipolar only processes, but Bipolar-CMOS-DMOS(BCD) processes have been adapted recently to fabricate these devices since most foundry companies have provided BCD processes instead of Bipolar only processes. In this study, Regulator and OP Amp are used as most popular design IPs and BCD processes for the designing are converted from bipolar only processes. Power Switching Sensor(PSS) ICs are designed specifically and fabricated on a silicon chip. The operation results of the packaged chip show the good matching with test results of the simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1A
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• pp.58-64
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• 2006

A 900-MHz band transceiver has been developed for RFID reader applications. In the transmitter, a GaAs SPST switch is used for high speed switching and low power consumption. In the receiver, a double balanced mixer is used to compress even-harmonic products. The ASK demodulator which consists of an active filter and comparator is used to reject the unwanted in band interferers. The transceiver produces a maximum transmitting power of 30 dBm and exhibits an 5 m communication range with a 6-dBi gain antenna.

• Journal of the Korean Institute of Telematics and Electronics
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• v.12 no.6
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• pp.21-30
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• 1975

A method by which one can optimize the complex responses of electronic circuits has been suggested. represented in the complex forms, the optimization methods presented so far have dealt with real magnitude and phase responses of circuits. Design examples are shown on the optimal designs of an amplifier, filter, operational circuits transmission lines. and a wave-shaping circuit.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.11
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• pp.872-879
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• 2017

This work presents a cable fault monitoring system based on the differential frequency domain reflectometry using a compact impedance analyser which is composed of a direct digital synthesizer, an op amp and a gain/phase detector with a micro controller. The proposed system can replace expensive vector network analysers for frequency domain reflectometry and therefore be deployed in sensor networks for long term multi-point cable monitoring. Effectiveness of the system is experimentally confirmed by diagnosing the status of the power cable.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2018.06a
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• pp.28-30
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• 2018

본 논문에서는 전이중 통신 방식을 사용하는 DOCSIS 3.1 시스템의 자기간섭 제거를 위한 자기간섭신호의 채널 및 비선형 왜곡 요소를 추정하는 기술을 제안한다. DOCSIS 3.1 시스템의 전이중 통신 방식은 일반적으로 가입자 단말인 CM (Cable Modem) 과 케이블방송신호 송신 시스템인 CMTS (Cable Modem Termination System) 사이의 상하향 통신을 시간/주파수의 분할 없이 동시에 수행하는 통신 방식이다. CMTS 에서 CM 의 신호를 수신함과 동시에 CMTS 신호를 송신하는 경우 고출력의 CMTS 송출신호가 CMTS 의 수신기로 인가되는 자기간섭 현상이 발생하게 된다. 이렇게 인가되는 자기간섭신호는 고출력 증폭기 (HPA: High - Power Amplifier) 및 Feedback 채널의 영향으로 크게 왜곡되어 수신된다. 따라서 자기간섭신호를 제거하고 CM 의 신호를 원활하게 복조하기 위해서는 자기간섭신호의 왜곡 요소룰 추정 및 보상하는 절차가 반드시 필요하다. 본 논문에서는 자기간섭신호의 HPA 에서 발생하는 비선형 왜곡 요소 및 Feedback 채널의 영향으로 발생하는 채널 요소를 추정하는 기술을 제안하고 성능을 분석한다. 제안된 기술은 간단한 연산기반으로 왜곡요소의 추정이 가능하며 반복추정을 통해 성능을 효과적으로 향상시키는 것이 가능하다.