• Journal of Digital Contents Society
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• v.19 no.2
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• pp.343-349
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• 2018

The proposed hybrid algorithm combines the benefits of rapid convergence property of mean filed annealing(MFA) and the effective genetic operations of simulated annealing-like genetic algorithm(SGA). This algorithm is applied to the isotropic material stock cutting problem, especially to glass cutting in distributed computing environments base on MPI called message passing interface. The glass cutting is to place the required rectangular patterns to the given large glass sheets resulting in reducing the wasted scrap area. Our experimental results show that the heuristic method improves the performance over the conventional ones by decreasing the scrap area and maximum execution time. It is also proved that the proposed distributed algorithm maintains the convergence properties of sequential one while it achieves almost linear speedup as the problem size increases.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.46-54
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• 1999

The output values of cellular neural networks would have errors because they can be stabilized at local minimums depending on the initial states of each cell. So, in this paper, we design the $6\times6$cellular neural networks with annealing capability which guarantees that the outputs reaches the global minimum to have correct output values independent of the initial states of each cell. This chip is designed using a $0.8\mu\textrm{m}$ CMOS technology The designed chip contains about 15,000 transistors and the chip size is about $2.89\times2.89\textrm{mm}^2$. The simulation results of edge extraction and hole filling using the designed circuit show that the outputs values would have errors in un-annealed case, but not in annealed case. In the simulation, the annealing time of $3\musec$ is employed.

• Journal of the Korea Society for Simulation
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• v.20 no.4
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• pp.59-66
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• 2011

This work presents an algorithm for generating multi-RUN (m-RUN) deadlock avoidance policy based on simulated annealing algorithm. The basic idea of this method is to gradually improve the current m-RUN DAP after constructing an initial m-DAP by using simple m RUN DAPs. The search for a neighbor of the current m-RUN DAP is done by selecting and changing only one component of the current m-RUN, while accepting some unimproved solutions with some probability. It is examined for its performance by generating some sample system configurations.

• Journal of the Korean Chemical Society
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• v.64 no.6
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• pp.345-349
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• 2020

In the self-assembled monolayer (SAM) of alkanethiol formed on a gold surface, some molecules fail to chemisorb with their terminal alkyl groups physisorbed. The previous molecular dynamics (MD) simulation showed that these defects can be cured by thermal annealing. Herein, we present a simple Ising model of alkanethiol. The Monte Carlo simulation based on the present model reproduced the essential features of the annealing of SAM observed in the MD simulation.

• Journal of Internet of Things and Convergence
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• v.9 no.3
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• pp.93-98
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• 2023

In this paper, an artificial neural network based on simulated annealing was constructed. The mapping relationship between the parameters of micro-scaled flow channels electrochemical machining and the channel shape was established by training the samples. The depth and width of micro-scaled flow channels electrochemical machining on stainless steel surface were predicted, and the flow channels experiment was carried out with pulse power supply in NaNO3 solution to verify the established network model. The results show that the depth and width of the channel predicted by the simulated annealing artificial neural network with "4-7-2" structure are very close to the experimental values, and the error is less than 5.3%. The predicted and experimental data show that the etching degree in the process of channels electrochemical machining is closely related to voltage and current density. When the voltage is less than 5V, a "small island" is formed in the channel; When the voltage is greater than 40V, the lateral etching of the channel is relatively large, and the "dam" between the channels disappears. When the voltage is 25V, the machining morphology of the channel is the best.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.8
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• pp.486-494
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• 2006

In this paper, we introduce a new solution for the load balancing problem, an important issue in parallel processing. Our heuristic load balancing technique called MGA effectively combines the benefit of both mean-field annealing (MFA) and genetic algorithms (GA). We compare the proposed MGA algorithm with other mapping algorithms (MFA, GA-l, and GA-2). A multiprocessor mapping algorithm simulation has been developed to measure performance improvement ratio of these algorithms. Our experimental results show that our new technique, the composition of heuristic mapping methods improves performance over the conventional ones, in terms of solution quality with a longer run time.

• Journal of the Korea Society for Simulation
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• v.24 no.4
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• pp.77-88
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• 2015

In this paper, we consider a two-agent single-machine scheduling problem with exponential job-dependent position-based learning effects. The objective is to minimize the total weighted completion time of one agent with the restriction that the makespan of the other agent cannot exceed an upper bound. First, we propose a branch-and-bound algorithm by developing some dominance /feasibility properties and a lower bound to find an optimal solution. Second, we design an efficient simulated annealing (SA) algorithm to search a near optimal solution by considering six different SAs to generate initial solutions. We show the performance superiority of the suggested SA using a numerical experiment. Specifically, we verify that there is no significant difference in the performance of %errors between different considered SAs using the paired t-test. Furthermore, we testify that random generation method is better than the others for agent A, whereas the initial solution method for agent B did not affect the performance of %errors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.5
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• pp.42-49
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• 2007

This paper introduces a study on reliability-driven device placement using simulated annealing algorithm which can be applicable to MCM or electronic systems embedded in a spacecraft running at thermal conduction environment. Reliability of the unit's has been predicted with the devices' junction temperatures calculated from FDM solver and optimized by simulated annealing algorithm. Simulated annealing in this paper adopts swapping devices method as a perturbation. This paper describes and compares the optimization simulation results with respect to two objective functions: minimization of failure rate and minimization of average junction temperature. Annealing temperature variation simulation case and equilibrium coefficient variation simulation case are also presented at the two respective objective functions. This paper proposes a new approach for reliability optimization of MCM and electronic systems considering those simulation results.

• The Transactions of the Korea Information Processing Society
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• v.6 no.9
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• pp.2311-2319
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• 1999

We present two heuristic algorithms for the task allocation problem (NP-complete problem) in parallel computing. The problem is to find an optimal mapping of multiple communicating tasks of a parallel program onto the multiple processing nodes of a distributed-memory multicomputer. The purpose of mapping these tasks into the nodes of the target architecture is the minimization of parallel execution time without sacrificing solution quality. Many heuristic approaches have been employed to obtain satisfactory mapping. Our heuristics are based on genetic algorithms and simulated annealing. We formulate an objective function as a total computational cost for a mapping configuration, and evaluate the performance of our heuristic algorithms. We compare the quality of solutions and times derived by the random, greedy, genetic, and annealing algorithms. Our experimental findings from a simulation study of the allocation algorithms are presented.

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1627-1629
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• 1997

엑시머 레미저를 이용한 다결정 실리콘막과 게이트 절연막 사이의 계면 거칠기를 개선하기 위해 변형핀 방법의 레이저 어닐링으로 다결정 실리콘 박막 트랜지스터를 제작하였다. SEM(scanning electron microscope)으로 활성층과 게이트 절연층과의 표면 이미지를 관찰한 결과 기존의 레이저 어닐링 결정화에 의한 것보다 계면 거칠기 정도가 상당히 줄었음을 관찰 하였다. 이렇게 개선된 계면 거칠기가 다결정 박막 트랜 지스터의 성능에 미치는 효과를 분석하기 위해 기존의 방법으로 제작된 소자와 계면 거칠기를 줄인 소자의 여러 가지 전기적 변수들(문턱 전압 기울기, 문턱 전압, 누설 전류)을 비교해 보았다. 우리는 또한 계면 거칠기와 다결정 박막 트랜지스터 소자의 상관 관계를 보기 위해 컴퓨터 시뮬레이션도 함께 병행하였다. 시뮬레이션을 통해 거친 계면 부근의 전계 집중 효과 같은 것으로 인해 소자의 성능이 저하된다는 것을 알 수 있었다.