• Proceedings of the Korean System Dynamics Society
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• 2000.07a
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• pp.49-61
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• 2000

본 논문에서는 정책개입시기를 이해하고 논의하는데 있어서 시스템 다이내믹스 학자들의 연구가 어떠한 시사점을 줄 수 있는가에 관하여 논의한다. 정책 시스템을 피드백 루프를 중심으로 하여 양의 피드백 루프가 지배하는 시스템, 음의 피드백 루프가 지배하는 시스템, 음과 양의 피드백 루프가 지배하는 시스템을 구분한다. 그리고 각 시스템에 있어서 바람직한 정책 개입의 시기에 관하여 논의하고, 어떠한 인지적 편향과 제도적 장애가 있는지를 논의한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.74-80
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• 2006

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise performance. The proposed PLL has two Charge Pump (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppress the voltage fluctuation of LF. In result, it improves phase noise characteristic. The Proposed PLL has been fabricated with 0.35fm 3.3V CMOS process. Measured phase noise at 1-MHz offset is -103dBc/Hz resulting in a minimum 3dBc/Hz phase noise improvement compared to the conventional PLL.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2000.11a
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• pp.15-23
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• 2000

If a system such as a port and regional economy has a large boundary and complexity, the system's substance is considered as a black box, forecast accuracy will be very low. Futhermore various components in a port and regional economy exert significant influence on each other. To copy with these problem the form of structure models were introduced by using SD model. This study has the issue of simplifying the regional economic effects of the port as contributing to raising the regional income. The regional economic effects of port have various indirect ones except for this. So, SD(System Dynamics) was presented, and applied to simulate port and regional economy.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.82-88
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• 2014

An available capacitance increasing phase-locked loop(PLL) with two voltage controlled oscillator gains has been proposed. In this paper, the available capacitance of loop filter is increased by using two positive/negative gains of voltage controlled oscillator (VCO). It results in 1/10 reduction in the size of loop filter capacitor. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and a locking time of conventional PLL.

• Journal of the Korean Institute of Gas
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• v.9 no.1 s.26
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• pp.33-37
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• 2005

This paper deals with parametric studies for the structural response of LNG Storage Tank steel roof behavior acoording to change in design condition. In the design of steel roof, it may be required to represent a stable behavior under many loading conditions and those of combinations. We fulfill the analysis the steel roof behavior during concret placing and additionally change the design variabls like H beam, pressure and steel roof plate thickness. On the basis of the obtained results from this studies a guideline for a more reasonable design of LNG storage tank steel roof is introduced.

• Journal of KIISE:Software and Applications
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• v.29 no.11
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• pp.826-836
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• 2002

We need an enormous amount of memories for name spaces as well as additional processors if we are to effectively exploit a massively parallelism in nested loops of functional languages such as Id. If there is no sufficient amount of memories enough to exploit that parallelism, the execution of programs can be aborted during the unfolding of loops. Additionally, if loops are overunfolded, compared with the number of processors available, the system performance can be degraded severely due to the overhead of loop unfolding. This paper suggests and analyzes an algorithm which can be used to effectively unfold nested loops of functional languages on multithreaded architectures. This algorithm has a feature to unfold a given nested loop safely and near optimally, considering the system resources of processors and memories available when the loop is to be unfolded.

• Proceedings of the KIEE Conference
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• 1999.07c
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• pp.1142-1144
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• 1999

본 논문에서는 최근 선진국에서 활발히 연구중인 EMF 차폐 대책의 일환인 수동 루프에 대한 이론적 분석 방법을 기술하고, 송전선로 자계 저감 효과를 실제 우리나라 345kV, 765kV를 대상으로 정량적 효과를 분석하였다. 그 결과 수동 루프를 적용한 경우, 약 30% 정도의 자계 저감 효과를 나타내어 전력설비의 유효한 대책임을 확인하였다.

• Korean System Dynamics Review
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• v.13 no.1
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• pp.113-131
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• 2012

Applying social network analysis techniques, this study examines complex system characteristics of industry-university joint research R&D networks. In specific, it focuses on whether these R&D networks comply with the power law, whose system typically presents the-rich-get-richer and the-poor-get-poor patterns. The basic data come from 7,751 industry-university joint research projects, all of which were carried out by Daejeon, Chungbuk, and Chungnam-based universities from January 2005 to October 2008. The empirical results reveal that the R&D networks abide by the power law. That is, a handful of business units and universities command an overwhelming majority in the joint links, indicating positive feedback dominance within the system.

• The Journal of the Acoustical Society of Korea
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• v.14 no.3
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• pp.28-36
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• 1995

In this paper, a double loop control model using leaky delay LMS algorithm are proposed for active noise control. The proposed double loop control model estimates the loudspeaker characteristic and the error path transfer function with on-line using only gain and acoustic time delay to reduce computation burden. The control of error signal through double loop control scheme makes the more robust cntrol system. The input signal of filter to estimate acoustic time delay is used difference between input signal of input microphone and adaptive filter output. And also, in nonstationary environments, the leaky delay LMS algorithm is employed to counteract parameter drift of delay LMS algorithm. For practical noise signal, the proposed double loop control model reduces noise level about 12.9 dB.

• The Journal of the Korea Contents Association
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• v.13 no.11
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• pp.347-355
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• 2013

This study analyzed President Lee's speeches of Korea and the policy of SMES and ventures in the field of information technology using cognitive map analysis. The relationship analysis between policy tool variables and policy goal variables was employed to derive policy direction of IT SMEs and ventures. This paper suggests growth competence reinforcement, investment revitalization, revitalization of start-up companies, enhancement of technology competition, globalization and job creation to the policy direction of IT SMEs and ventures. In this paper, we constructed a cognitive map on the policy vision of SMEs and ventures in the field of information technology. This study also showed that this cognitive map could be characterized by a scarcity of feedback loops and a strong emphasis on the positive loops in the structure of virtuous circle.