• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.10
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• pp.595-600
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• 2016

In this paper, the oxide currents of thin silicon oxides is investigated. The oxide currents associated with the on time of applied voltage were used to measure the distribution of voltage stress induced traps in thin silicon oxide films. The stress induced leakage currents were due to the charging and discharging of traps generated by stress voltage in the silicon oxides. The stress induced leakage current will affect data retention in memory devices. The oxide current for the thickness dependence of stress current and stress induced leakage currents has been measured in oxides with thicknesses between $109{\AA}$, $190{\AA}$, $387{\AA}$, and $818{\AA}$ which have the gate area $10^{-3}cm^2$. The oxide currents will affect data retention and the stress current, stress induced leakage current is used to estimate to fundamental limitations on oxide thicknesses.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.383-386
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• 1988

In MOS integrated circuits, annealing after oxidation process is necessary to improve physical properties of silicon dioxide. With subsequent annealing in inert gases such as nitrogen or argon, and excess silicon bond is allowed time to complete the oxidation and surface charge density is reduced. In this paper, we will present effects of the rapid thermal annealing on silicon dioxide. In order to evaluate characteristics of silicon dioxide, we analyzed C-V curve dependent on annealing time and temperature, and presented variation of fixed oxide charge.

• Korean Journal of Materials Research
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• v.7 no.7
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• pp.582-586
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• 1997

본 연구에서는 플라즈마 화학 증착법으로 기판에 따른 DLC 박막의 접착력 변화를 조사하였다. 박막의 분리가 발생하기 시작하는 경우의 두께를 임계두께로 정하여 스크래치 테스터로 측정된 임계하중과 더불어 박막의 잡착강도값으로 사용하였다. 다이아몬드상 탄소박막은 실리콘 기판에서 가장 우수한 접착력을 가지는 것으로 나타났으며, 크롬>티타늄>철>세라믹 기판의 순으로 접착력이 감소하였다. XPS, AES 분석을 사용하여 계면에서 결합구조와 결합형태 등을 관찰하여 접착력과의 관계를 조사하였다. 그 결과 다이아몬드상 탄소박막의 접착강도는 막/기판의 계면에서의 탄화물 형성에 영향을 받으며, 계면에서의 초기산화물층에 큰 영향을 받는것을 확인하였다.

• Journal of the Korean Ceramic Society
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• v.31 no.1
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• pp.74-78
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• 1994

Degradation of thin oxide by doped poly-Si and its improvement were studied. The gate oxide can be degraded by phosphorous in poly-Si doped POCl3. The degradation is increased with the decrement of sheet resistance and poly-Si thickness. Oxide failures of amorphous-Si are higher than those of poly-Si. In-situ double deposition of amorphous-Si, 54$0^{\circ}C$/30 nm, and poly-Si, 6$25^{\circ}C$/220 nm, forms the mismatch structure of grain boundary between amorphous-Si and poly-Si, and suppresses the excess phosphorous on oxide surface by the mismatch structure. The control of phosphorous through grain boundary improves the oxide reliability.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.4
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• pp.361-366
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• 2004

The interface stability of Ta-Mo alloy film on SiO$_2$ was investigated. Ta-Mo alloy films were formed by co-sputtering method, and the alloy composition was varied by controlling Ta and Mo sputtering power, When the atomic composition of Ta was about 91％, the measured work function was 4.24 eV that is suitable for NMOS gate. To identify interface stability between Ta-Mo alloy film and SiO$_2$, C-V and XRD measurements were performed on the samples annealed with rapid thermal processor between $600^{\circ}C$ and 90$0^{\circ}C$. Even after 90$0^{\circ}C$ rapid thermal annealing, excellent interface stability and electrical properties were observed. Also, thermodynamic analysis was studied to compare with experimental results.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.168-169
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• 2005

실온에서 디스플레이 응용을 위하여 ICP CVD로 PET기판 위에 실리콘 산화 반사 방지막을 성장시키고, EDXA로 분석하였다. 분광 Ellipsometer, UV-V와 FTIR분광기를 이용하여 반사율을 3%이하까지 낮출 수 있다는 것을 확인하였고, SEM장비를 이용하여 표면 상태를 알아보았으며. Essential Macleod 광학디자인 프로그램을 이용한 시뮬레이션 결과와 일치함을 확인하였다. 본 연구결과를 이용하면 다층박막 대신 단층 반사방지막을 제작하여 경제적이고, 효과적인 반사방지막을 제작할 수 있다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.29-30
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• 2005

Experimental results are presented for the degradation of 3 nm-thick gate oxide ($SiO_2$) under both Negative-bias Temperature Instability(NBTI) and Hot-carrier-induced(HCI) stresses using P and NMOSFETs that are annealed with hydrogen or deuterium gas at high-pressure (1~5 atm.). Statistical parameter variations depend on the stress conditions. We suggest that deuterium bonds in $SiO_2$ film is effective in suppressing the generation of traps related to the energetic hot electrons.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.814-819
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• 1986

In this work the electrical conduction and breakdown properties of thermal oxides grown on phosphorus-doped polysilicon have been investigated by using ramped I-V measurements. The oxide films, grown from phosphorus-doped polysilicon deposited at 560\ulcorner, have higher breakdown field(6.8MV/cm) and lower leakage current than those deposited at 625\ulcorner. Also the effective energy barrier height(\ulcorner)calculated from the Fowler-Nordheim curve of polyoxide was 0.76eV for 560\ulcorner deposited film and 0.64eV for 625\ulcorner deposited film.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.1
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• pp.39-49
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• 1999

Monolayer thick fluorocarbon films were characterized by the contact angle measurements. The contact angles of three different liquids, water, formamide and diiodomethane were measured on spun coated, vapor phased deposited films and Teflon surface. The highest contact angle over $130^{\circ}$was observed on fluorocarbon films deposited on Al substrates while the lowest angles below $70^{\circ}$deposited on oxide. The surface energies were calculated based on Lewis acid /base theory. The surface energies of Teflon and spin coated FC films were calculated to have 18 and 8.4 dynes /cm, respectively. Higher energies of 31 to .35 dynes /cm were calculated on vapor phase deposited films on silicon and oxide. However vapor phase deposited films on aluminum only showed a large Lewis base energy term. It might be explained by the surface roughness and heterogeneity as observed by dynamic contact angles and AFM measurements.

• Journal of the Korean Vacuum Society
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• v.20 no.1
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• pp.63-69
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• 2011

In this study, we report on the novel lithographic patterning method to fabricate organic thin film field effect transistors (OTFTs) based on photo and e-beam lithography with well-known silicon technology. The method is applied to fabricate pentacene-based organic field effect transistors. Owing to their solubility, sub-micron sized patterning of P3HT and PEDOT has been well established via micromolding in capillaries and inkjet printing techniques. Since the thermally deposited pentacene cannot be dissolved in solvents, other approach was done to fabricate pentacene FETs with a very short channel length (~30 nm), or in-plane orientation of pentacene molecules by using nanometer-scale periodic groove patterns as an alignment layer for high-performance pentacene devices. Here, we introduce $Al_2O_3$ film grown via atomic layer deposition method onto pentacene as a passivation layer. $Al_2O_3$ passivation layer on OTFTs has some advantages in preventing the penetration of water and oxygen and obtaining the long-term stability of electrical properties. AZ5214 and ma N-2402 were used as a photo and e-beam resist, respectively. A few micrometer sized lithography patterns were transferred by wet and dry etching processes. Finally, we fabricated micron sized pentacene FETs and measured their electrical characteristics.