• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.9
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• pp.1028-1036
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• 2008

In the OFDM system, IQ imbalance problem happens at the RF front-end of transceiver, which degrades the BER(bit error rate) performance because it affects the constellation in the received signal. Also, phase noise is generated in the local oscillator of transceivers and it destroys the orthogonality between the subcarriers. Conventional PNS algorithm is effective for phase noise suppression, but it is not useful anymore when there are jointly IQ(In-phase and Quadrature) imbalance and phase noise. Therefore, in this paper, we analyze the effect of IQ imbalance and phase noise generated in the down-conversion of the receiver. Then, we estimate and compensate the IQ imbalance and phase noise at the same time. Compared with the conventional method that IQ imbalance after IFFT is estimated and compensated in front of FFT via the feedback, this proposed method extracts and compensates effect of IQ imbalance after FFT stage. In case IQ imbalance and phase noise exist at the same time, we can decrease complexity because it is needless to use elimination of IQ imbalance in time domain and training sequences and preambles. Also, this method shows that it reduces the ICI and CPE component using adaptive forgetting factor of MMSE after FFT.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.1-9
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• 2009

In this paper, a small area 12-bit 300MSPS CMOS Digital-to-Analog Converter(DAC) is proposed for display systems. The architecture of the DAC is based on a current steering 6+6 segmented type, which reduces non-linearity error and other secondary effects. In order to improve the linearity and glitch noise, an analog current cell using monitoring bias circuit is designed. For the purpose of reducing chip area and power dissipation, furthermore, a noble self-clocked switching logic is proposed. To verify the performance, it is fabricated with $0.13{\mu}m$ thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective chip area is $0.26mm^2$ ($510{\mu}m{\times}510{\mu}m$) with 100mW power consumption. The measured INL (Integrated Non Linearity) and DNL (Differential Non Linearity) are within ${\pm}3LSB$ and ${\pm}1LSB$, respectively. The measured SFDR is about 70dB, when the input frequency is 15MHz at 300MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.1
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• pp.132-139
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• 2016

This study was carried out near the waters of Jango port, Dangjin-gun, Chungcheongnam-do by utilizing 10kHz carrier frequency, for the purpose of measurement and analysis of underwater channel environment of the Western sea. For the measurement of horizontal channel environment, the separation distance between transmitter and receiver is made differently in the range between 10m and 4000m. Meanwhile, for the measurement of vertical channel environment, transmission and receiving side ships are fixed as contacted each other and measured differently depending on their depth of submergence. In this study, the Coherence Bandwidth and the Coherence Time were estimated by analyzing the Power delay profile of the real sea based on the measured data, and analyzing the doppler frequency through frequency conversion of received tone-signal, respectively. This study is expected to become a base study in carrying out the frame design for underwater communication to improve the communication and secure the reliability of communication in future underwater channel environment.

• Journal of Advanced Navigation Technology
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• v.26 no.4
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• pp.211-218
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• 2022

Continuous wave (CW) radar has the advantage of reliability and accuracy compared to other sensors such as camera and lidar. In addition, binarized neural network (BNN) has a characteristic that dramatically reduces memory usage and complexity compared to other deep learning networks. Therefore, this paper proposes binarized neural network based human identification and motion classification system using CW radar. After receiving a signal from CW radar, a spectrogram is generated through a short-time Fourier transform (STFT). Based on this spectrogram, we propose an algorithm that detects whether a person approaches a radar. Also, we designed an optimized BNN model that can support the accuracy of 90.0% for human identification and 98.3% for motion classification. In order to accelerate BNN operation, we designed BNN hardware accelerator on field programmable gate array (FPGA). The accelerator was implemented with 1,030 logics, 836 registers, and 334.904 Kbit block memory, and it was confirmed that the real-time operation was possible with a total calculation time of 6 ms from inference to transferring result.

• Journal of Advanced Navigation Technology
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• v.26 no.5
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• pp.365-372
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• 2022

Compared to sensors mainly used in human activity recognition (HAR) systems, inertial measurement unit (IMU) sensors are small and light, so can achieve lightweight system at low cost. Therefore, in this paper, we propose a binary neural network (BNN) based gait pattern analysis system using IMU sensor, and present the design and implementation results of an FPGA-based accelerator for computational acceleration. Six signals for gait are measured through IMU sensor, and a spectrogram is extracted using a short-time Fourier transform. In order to have a lightweight system with high accuracy, a BNN-based structure was used for gait pattern classification. It is designed as a hardware accelerator structure using FPGA for computation acceleration of binary neural network. The proposed gait pattern analysis system was implemented using 24,158 logics, 14,669 registers, and 13.687 KB of block memory, and it was confirmed that the operation was completed within 1.5 ms at the maximum operating frequency of 62.35 MHz and real-time operation was possible.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.8 no.6
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• pp.853-861
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• 2018

This paper proposes the application of harmonic constraints to address the problems caused by abnormal voltage increases when electric railway vehicles are running. The AC line that supplies the train with power during operation is used to provide electricity of 25kV/60 Hz, but gradually the size and frequency of harmonics involved in the line are varied with the technological evolution of the railroad vehicle electrical equipment. An increase in heat losses due to the failure of the instrument transformer (PT), the main circuit device, which is a serious problem with the recent train safety operation, or to the main displacement voltage. When high frequency components are introduced through low frequency Transformers of the main circuit device, the high intensity of the components is caused by the high intensity of the core and the current flow of the parasitic core is increased, thus generating heat. To solve this problem, the recent adjustment of the sequence has applied artificial NOTCH OFF of the power converter. However, the method of receiving and controlling the OFF signal operates by interaction between the ground and the vehicle's devices, thus it is invalid in the event of failure, and an actual accident is occurring. Therefore, the harmonic currents were required to prevent possible flow of harmonics, and conducted a study to prevent accidental occurrence of train accidents and to verify feasibility of the device through the simulations of the train's experimental analysis and the simulations of the train for safe operation.

• The Journal of the Acoustical Society of Korea
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• v.28 no.2
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• pp.119-126
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• 2009

This paper describes the non-stringed guitar composed of laser strings, frets, sound synthesis algorithm and a processor. The laser strings that can depict stroke and playing arpeggios comprise laser modules and photo diodes. Frets are implemented by voltage divider. The guitar body does not need to implement physically because commuted waveguide synthesis is used. The proposed frets enable; players to represent all of chords by the chord glove as well as guitar solo. Sliding, hammering-on and pulling-off sounds are synthesized by using parameters from the voltage divider. Because the pitch shifting corresponds to the time-varying propagation speed in the digital waveguide model, the proposed model can synthesize vibrato as well. After transformation of signals from the laser strings and frets into parameters for synthesis algorithm, the digital signal processor, TMS320F2812, performs the real-time synthesis algorithm and communicates with the DAC. The demonstration movieclip available via the Internet shows one to play a song, 'Arirang', synthesized by proposed algorithm and interfaces in real-time. Consequently, we can conclude that the proposed synthesis algorithm is efficient in guitar solo and there is no problem to play the non-stringed guitar in real-time.

• The Korean Journal of Nuclear Medicine
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• v.32 no.4
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• pp.365-373
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• 1998

Purpose: The conventional gamma camera is not ideal for scintimammography because of its large detector size (${\sim}500mm$ in width) causing high cost and low image quality. We are developing a small gamma camera dedicated for breast imaging. Materials and Methods: The small gamma camera system consists of a NaI (T1) crystal ($60 mm{\times}60 mm{\times}6 mm$) coupled with a Hamamatsu R3941 Position Sensitive Photomultiplier Tube (PSPMT), a resister chain circuit, preamplifiers, nuclear instrument modules, an analog to digital converter and a personal computer for control and display. The PSPMT was read out using a standard resistive charge division which multiplexes the 34 cross wire anode channels into 4 signals ($X^+,\;X^-,\;Y^+,\;Y^-$). Those signals were individually amplified by four preamplifiers and then, shaped and amplified by amplifiers. The signals were discriminated ana digitized via triggering signal and used to localize the position of an event by applying the Anger logic. Results: The intrinsic sensitivity of the system was approximately 8,000 counts/sec/${\mu}Ci$. High quality flood and hole mask images were obtained. Breast phantom containing $2{\sim}7 mm$ diameter spheres was successfully imaged with a parallel hole collimator The image displayed accurate size and activity distribution over the imaging field of view Conclusion: We have succesfully developed a small gamma camera using NaI(T1)-PSPMT and nuclear Instrument modules. The small gamma camera developed in this study might improve the diagnostic accuracy of scintimammography by optimally imaging the breast.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.