• 전기의세계
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• v.43 no.1
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• pp.20-22
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• 1994

이동통신은 그 방식이 아날로그든 디지틀이든 같은 기능의 음성신호를 송신하고 수신하는 것이다. 아나로그형은 크게 RF 수신부, RF 송신부, 신호처리부 제어부 그리고 전원부로 나누어 진다. 통화시 송,수신이 동시에 이루어지므로 송신신호와 수신신호가 서로 간섭하지 않도록 정교환 신호 여과기가 필요하다. Philips사의 경우 몇개의 칩으로 RF/IF 변환, 아나로그 신호처리 그리고 신호제어를 할 수 있도록 설계하였고 몇몇 선두회사들은 하나의 아나로그 처리기로 baseband 아나로그 신호를 처리 할 수 있도록 설계하였다. RF 부분은 아직 별도의 PCB에 제작되는데 이유는 IF 부분의 송.수신부가 공간을 많이 차지하며, RF 부분에는 가격을 내리기 위해 개별 소자들이 많이 쓰이기 때문이다.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.1
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• pp.23-28
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• 2016

In this paper, a Multi-Band Ku-band down converter was designed for reception of multi-band digital satellite broadcasting. The Multi-band low-nose down converter was designed to form four local oscillator frequencies (9.75, 10, 10.75 and 11.3GHz) representing a low phase noise due to VCO-PLL with respect to input signals of 10.7 to 12.75GHz and 3-stage low noise amplifier circuit by broadband noise matching, and to select an one band of intermediate frequency (IF) channels by digital control. The developed low-noise downconverter exhibited the full conversion gain of 64dB, and the noise figure of low-noise amplifier was 0.7dB, the P1dB of output signal 15dBm, and the phase noise -73dBc@100Hz at the band 1 carrier frequency of 9.75GHz. The low noise block downconverter (LNB) for receiving four-band digital satellite broadcasting designed in this paper can be used for satellite broadcasting of vessels navigating international waters.

• The Bulletin of The Korean Astronomical Society
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• v.43 no.1
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• pp.69.3-69.3
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• 2018

한국우주전파관측망(KVN, Korean VLBI Network)의 86 GHz 대역 수신기는 VLBI에서 주로 관측하는 85-95 GHz 주파수 대역에서 동작하도록 설계, 제작되었다. UMASS(University of Massachusetts) 대학으로부터 도입된 수신기의 대역폭을 84-116 GHz로 확장하기 위해 2017년도부터 수신기 설계, 부품 구입 등을 진행하고 있다.기존 수신기의 대역폭을 확장하기 위해, 협대역 주파수 변환기의 설계를 변경해야 한다. 주파수 변환기는 일반적으로 사용되는 SSB(Single Side Band) Mixer를 사용하지 않았다. 그 대신에 20 dB 이상의 높은 이미지 제거율을 갖도록 HPF(High Pass Filter)와 LPF(Low Pass Filter)를 사용하여 RF 주파수를 84-100 GHz와 100-116 GHz로 나눈 후 주파수 변환토록 하였다. 사용된 Filter의 특성을 이용, 이미지 대역 신호를 수 십 dB 이상 제거할 수 있다. RF 단에서의 신호 분리로 인해 수신기 등가잡음 온도는 수 K 정도 증가한다. 2017년에 제안된 주파수 변환기를 상온에서 구성하여 그 가능성을 검증하였고, 2018년 9월 까지 KVN W-band 수신기 1 대의 업그레이드를 진행할 것이다. 2019년까지 KVN 3 사이트의 W-band 수신기 주파수 확장을 완료할 계획이다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.8
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• pp.1188-1195
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• 2022

The 6-port phase correlator consists of one in-phase power divider and three 3-dB 90-degree phase difference power dividers, and is mainly used in a demodulation circuit that determines the phase of an input signal. This paper proposes the wideband 6-port phase correlator that consists of an in-phase power divider using a wideband 2:1 impedance transformer with three 37.5-Ω coaxial cables, and a 3-dB 90-degree phase difference power divide using Wireline. The proposed wideband phase correlator fabricated at a center frequency of 1000MHz has the value of the input reflection coefficient(S₁₁ and S₂₂) -14dB or less in the frequency range of 640~1270MHz. Also, the signal transmission characteristic(S_i1), from the in-phase power divider input port to four output ports, has the amplitude of -6.5±0.6dB and the phase error of within ±3.4°, and the signal transmission characteristic(S_i2), from the 90 degree phase difference power divider input port to four output ports, has the amplitude of -6.1±0.6dB and the phase error of within ±6.2°.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.11
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• pp.2081-2093
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• 1994

In this study, we design and implement 64 QAM demodulator which has 155 Mbps, first level of CCITT G707 SDH(Synchronous Digital Hierachy) for STM 1 signal transmission. Carrier recovery which effects the demodulator performance uses decision feedback carrier using 8 bits A/D converter. Also, PSF(Pulse Shaping Filter) is 7 order elliptic filter. Carrier recovery circuit is designed and implemented digital type which use high 3 bits of 8 bits conversion data as data and the order low bits as error data and hybrid type which use VCO and analog integrator. Therefore we obtain stable performance recovery.

• Journal of Broadcast Engineering
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• v.1 no.1
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• pp.1-6
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• 1996

Digital DBS service using Korea Sat starts at Korea Telecom's Yong-in transmission site. Total 6 transmitting stations are needed. At each transmitting station, 4 TV programs are compressed and multiplexed using MPEG-2, modulated into IF, RF signals, then finally transmitted through antenna. At DBS transponder, received signal is down converted, amplified and re-transmitted to earth. At receiver, signal is received by 45cm dish antenna, then wanted program is selected, demultiplexed and decoded. Transmission performance of BER lOE-ll is implemented by using FEe coding and QPSK modulation. For pay TV management, conditional access system, smart card and modem are used.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.2
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• pp.169-179
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• 1999

In this paper, a GaAs MESFET single-ended resistive mixer with high linearity and isolation is designed. The bias voltage of this mixer is applied only gate of GaAs MESFET to use the channel resistance. The LO is applied the gate and the RF is applied the drain through 7-pole hairpin bandpass filter to obtain the proper isolation thru LO-RF. The IF is extracted from the source with short circuit and lowpass filter. Using extracted equivalent circuits for LO and RF, conversion loss is calculated and compared with result of harmonic balance analysis. Measured conversion loss of this S-band down converter mixer is 8.2~10.5dB by considering the measured 3.0~3.4dB RF 7-pole hairpin bandpass filter loss and IP3in is 26.5dBm at Vg=-0.85~-1.0V in distortion performance.

• Journal of IKEEE
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• v.24 no.4
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• pp.1058-1063
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• 2020

This paper proposes a 12-bit SAR A/D(Successive Approximation Register Analog-to-Digital) converter that operates at low power for bio-signal and sensor signal processing. The conventional SAR A/D converter utilized the reduction of the dynamic current, which resulted in reducing total power consumption. In order to solve the limitation of the sampling time due to charging/discharging of the capacitor for reducing dynamic current, the different sampling time on the C-DAC bit switch operation was applied to reduce the dynamic current. In addition, lowering the supply voltage of the digital block to 0.6V led to 70% reduction of the total power consumption of the proposed ADC. The proposed SAR A/D was implemented with CMOS 65nm process 1-poly 6-metal, operates with a supply voltage of 1.2V. The simulation results demonstrate that ENOB, DNL/INL, power consumption and FoM are 10.4 bits, ±0.5LSB./±1.2LSB, 31.2uW and 2.8fJ/step, respectively.

• Journal of the Korean Society for Nondestructive Testing
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• v.26 no.2
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• pp.99-107
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• 2006

Magnetic nondestructive testing is very useful far detecting a crack on the surface or near of the surface of the ferromagnetic materials. The distribution of the magnetic flux leakage (DMFL) on a specimen has to be obtained quantitatively to evaluate the crack. The magnetic camera is proposed to obtain the DMFL at the large lift-off. The magnetic camera consists of a magnetic source, magnetic lens, analog to digital converters (ADCs), interface, and computer. The magnetic leakage fields or the distorted magnetic fields from the object, which are concentrated on the magnetic lens, are converted to analog electrical signals tv arrayed small magnetic sensors. These analog signals are converted to digital signals by the ADCs, and are stored, imaged, and processed by the interface and computer. However the magnetic camera has limitations with respect to converting and switching speed, full range and resolution, direct memory access (DMA), temporary storage speed and volume because common ADCs were used. Improved techniques, such as those that introduce the operational amplifier (OP-Amp), amplify the signal, reduce the connection line, and use the low pass filter (LPF) to increase the signal to noise ratio are necessary. This paper proposes the exclusive embedded ADC including OP-Amp, LPF, microprocessor and DMA circuit for the magnetic camera to satisfy the conditions mentioned above.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.826-832
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• 2004

A CMOS 8 bit folding and interpolating ADC for an embedded system inside VLSI is presented in this paper. This folding ADC uses the 2 stage architecture for improving of nonlinearity. repeating the folding and interpolating twice. At a proposed structure, a transistor differential pair operates on the second folder. A ADC with 2 stage architecture reduces the number of comparators and resisters. So it is possible to provide small chip size, low power consumption and high operating speed. The design technology is based on fully standard 0.25m double-Poly 2 metal n-well CMOS Process. The simulated Power consumption is 45mW with an applied voltage of 2.5V and sampling frequency of 250MHz. The INL and DNL are within <ㅆㄸㅌ>$\pm$0.2LSB, respectively. The SNDR is approximately 45dB for input frequency of 10MHz.