• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.431-441
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• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• Journal of Advanced Navigation Technology
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• v.22 no.5
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• pp.384-390
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• 2018

This paper introduces a MATLAB graphical user interface (GUI) based software for analysis of korea augmentation satellite system (KASS) availability performance. This software uses minimum variance (MV) estimator and Kriging algorithm to generate integrity information such as user differential range error (UDRE) and grid ionospheric vertical error (GIVE). The information is offered to ground and aviation users in Korean region. The software also gives accuracy data, protection level data and availability map about each user position by using the integrity information. In particular the software calculates the protection level along a path of aircraft. We verified the result of protection level of aviation user by comparing them with the results of SBASimulator#2, which is a simulation tool of european geostationary navigation overlay service (EGNOS). As a result, the protection level error between the result of our software and the SBASimulator#2 was about 2% which means that the result of our software is accurate.

• The KIPS Transactions:PartC
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• v.17C no.1
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• pp.1-14
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• 2010

IEEE 802.15.4[1] has been standardized for the physical layer and MAC layer of LR-PANs(Low Rate-Wireless Personal Area Networks) as a technology for operations with low power on sensor networks. The standardization is applied to the variety of applications in the shortrange wireless communication with limited output and performance, for example wireless sensor or virtual wire, but it includes vulnerabilities for various attacks because of the lack of security researches. In this paper, we analyze the vulnerabilities against the denial of sleep attacks on the MAC layer of IEEE 802.15.4, and propose a detection mechanism against it. In results, we analyzed the possibilities of denial of sleep attacks by the modification of superframe, the modification of CW(Contention Window), the process of channel scan or PAN association, and so on. Moreover, we comprehended that some of these attacks can mount even though the standardized security services such as encryption or authentication are performed. In addition to, we model for denial of sleep attacks by Beacon/Association Request messages, and propose a detection mechanism against them. This detection mechanism utilizes the management table consisting of the interval and node ID of request messages, and signal strength. In simulation results, we can show the effect of attacks, the detection possibility and performance superiorities of proposed mechanism.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.4
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• pp.1-10
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• 2011

According to the worldwide efforts to reduce greenhouse gases consequent upon climatic change, the field of road traffic is also making diverse efforts to reduce the emissions of greenhouse gases. Among these, the exhaust gases from vehicles, the so-called main culprit of the greenhouse gases will take place the more as delay and tie-up of vehicles ever take place. Accordingly, as a scheme for reducing the delay & tie-up of vehicles, it's possible to bring up the idea of supply of new facilities and management of the existing facilities; recently, a lot more focus is being put on the management of the existing facilities due to enormous amounts of construction cost. In the midst of growing concern for traffic demand management policy, it's about the time we should do research on the tollbooth metering on the expressway whose research is almost non-existent home and abroad. As a traffic demand management policy coming to happen in case of the management of pay expressway like Japan and Korea, this research analyzed the contents of tollbooth metering, its effect and its subsequent convenience. Especially as a tool for effect analysis, this research made an analysis using VISSIM-a micro-simulation tool. As the tollbooth metering promoted, as a part of green traffic promotion strategy, is expected to contribute to improvement in traffic flow and reduction in carbon emissions, etc. It seems that there needs to be continuous research work on the management plan & revitalization plan for maximization of its effect later as well.

• Journal of IKEEE
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• v.24 no.1
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• pp.25-32
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• 2020

In this paper, we propose an image generator for OLED panel test that can compensate for color coordinates and luminance by using panel defect inspection and optical measurement while displaying images on OLED panel. The proposed image generator consists of two processes: the image generation process and the process of compensating color coordinates and luminance using optical measurement. In the image generating process, the panel is set to receive the panel information to drive the panel, and the image is output by adjusting the output setting of the image generator according to the panel information. The output form of the image is configured by digital RGB method. The pattern generation algorithm inside the image generator outputs color and gray image data by transmitting color data to a 24-bit data line based on a synchronization signal according to the resolution of the panel. The process of compensating color coordinates and luminance using optical measurement outputs an image to an OLED panel in an image generator, and compensates for a portion where color coordinates and luminance data measured by an optical module differ from reference data. To evaluate the accuracy of the image generator for the OLED panel test proposed in this paper, Xilinx's Spartan 6 series XC6SLX25-FG484 FPGA was used and the design tool was ISE 14.5. The output of the image generation process was confirmed that the target setting value and the simulation result value for the digital RGB output using the oscilloscope matched. Compensating the color coordinates and luminance using optical measurements showed accuracy within the error rate suggested by the panel manufacturer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1107-1114
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• 2004

System Packet Interface Level 4 Phase 2(SPI-4.2) is an interface for packet and cell transfer between a physical layer(PHY) device and a link layer device, for aggregate bandwidths of OC-192 ATM and Packet Over Sonet/SDH(POS), as well as 10Gbps Ethernet applications. SPI-4.2 core consists of Tx and Rx modules and supports full duplex communication. Tx module of SPI-4.2 core writes 64-bit data word and 14-bit header information from the user interface into asynchronous FIFO and transmits DDR(Double Data Rate) data over PL4 interface. Rx module of SPI-4.2 core operates in vice versa. Tx and Rx modules of SPI-4.2 core are designed to support maximum 256-channel and control the bandwidth allocation by configuring the calendar memory. Automatic DIP4 and DIP-2 parity generation and checking are implemented within the designed core. The designed core uses Xilinx ISE 5.li tool and is described in VHDL Language and is simulated by Model_SIM 5.6a. The designed core operates at 720Mbps data rate per line, which provides an aggregate bandwidth of 11.52Gbps. SPI-4.2 interface core is suited for line cards in gigabit/terabit routers, and optical cross-connect switches, and SONET/SDH-based transmission systems.

• Journal of IKEEE
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• v.19 no.2
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• pp.168-175
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• 2015

In this paper, we propose FPGA design technique for rotating LED display device which is capable of displaying videos with the use of the afterimage effect. The proposed technique is made up of image data correction process based on inverse gamma correction and error diffusion, block interleaving process, and data serial output process. The data correction process based on inverse gamma correction and error diffusion is an image data correction step in which image data received are corrected by inverse gamma correction process to convert the data into linear brightness characteristics, and by error diffusion process to reduce the brightness reduction phenomenon in low-gray-level which is caused by inverse gamma correction. In the block interleaving process, the data of the frames entered transversely are first saved in accordance with entrance order, and then only the longitudinal image data are read. The data serial output process is applied to convert the parallel data in a rotating location into serial data and send them to LED Driver IC, in order to send data which will be displayed on high-speedy rotating LED Bar. To evaluate the accuracy of the proposed FPGA design technique, this paper used XC6SLX45-FG484, a Spartan 6 family of Xilinx, as FPGA, and ISE 14.5 as a design tool. According to the evaluation analysis, it was found that goal values were consistent with simulation values in terms of accurate operation of inverse gamma and error diffusion correction, block interleaving operation, and serialized operation of image data.

• The KIPS Transactions:PartB
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• v.9B no.5
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• pp.571-578
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• 2002

In this paper, we propose a video sequence coding scheme called AMV (Auxiliary Motion Vector) to minimize error propagation caused by transmission errors over the Internet. Unlike the conventional coding schemes the AMY coder, for a macroblock in a frame, selects two best matching blocks among several preceding frames. The best matching block, called a primary block, is used for motion compensation of the destination macroblock. The other block, called an auxiliary block, replaces the primary block in case of its loss at the decoder. When a primary block is corrupted or lost during transmission, the decoder can efficiently and simply suppress error propagation to the subsequent frames by replacing the block with an auxiliary block. This scheme has an advantage of reducing both the number and the impact of error propagations. We implemented the proposed coder by modifying H.263 standard coding and evaluated the performance of our proposed scheme in the simulation. The simulation results show that AMV coder is more efficient than the H.263 baseline coder at the high packet loss rate.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.10
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• pp.600-608
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• 2016

This paper proposes a new high-efficient interleaved phase-shift full-bridge (PSFB) converter for low-voltage and high-current power systems. The proposed converter is composed of three switch-bridges and two transformers in the primary side and two rectifiers in the secondary side. Each transformer handles half of the total power with an interleaved operation, so that the proposed converter has high system reliability, as much as the conventional interleaved PSFB converter. The soft-switching characteristics of the proposed converter are better than those of the conventional converter due to the modulated primary side configuration. The proposed converter represents a single lagging-leg bridge, which has a poor soft switching condition in its operation, while the conventional converter has two lagging-leg bridges in its operation. Therefore, the number of switches having hard-switching conditions is reduced by half in the proposed converter. In addition, the reduced switch counts in the primary side of the proposed converter helps decrease the complexity of the proposed converter compared to that of the conventional converter. The operational principle and analysis are presented in this paper and the characteristics are verified using a PSIM simulation with 3kW server power specification.

• Journal of Technology Innovation
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• v.29 no.4
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• pp.1-30
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• 2021

Due to the recent development of system semiconductors, technical innovation for the electric devices of the automobile industry is rapidly progressing. In particular, the electric device of automobiles is accelerating technology development competition among automobile parts makers, and the development cycle is also changing rapidly. Due to these changes, the importance of strategic planning for R&D is further strengthened. Due to the paradigm shift in the automobile industry, the Product-Technical Roadmap (P/TRM), one of the R&D strategies, analyzes technology forecasting, technology level evaluation, and technology acquisition method (Make/Collaborate/Buy) at the planning stage. The product-technical roadmap is a tool that identifies customer needs of products and technologies, selects technologies and sets development directions. However, most companies are developing the product-technical roadmap through a qualitative method that mainly relies on the technical papers, patent analysis, and expert Delphi method. In this study, empirical research was conducted through simulations that can supplement and strengthen the product-technical roadmap centered on the automobile industry by fusing Gartner's hype cycle, cumulative moving average-based data preprocessing, and deep learning (LSTM) time series analysis techniques. The empirical study presented in this paper can be used not only in the automobile industry but also in other manufacturing fields in general. In addition, from the corporate point of view, it is considered that it will become a foundation for moving forward as a leading company by providing products to the market in a timely manner through a more accurate product-technical roadmap, breaking away from the roadmap preparation method that has relied on qualitative methods.